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document no. a13286ej1v0um00 (1st edition) date published july 1998 n cp(n) printed in japan 1998 ? preliminary users manual usb host controller m m m m PD9210FGC-7EA
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3 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
4 pc/at is a trademark of ibm corp. the application circuits and their parameters are for reference only and are not intended for use in actual design-ins. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. the information in this document is subject to change without notice. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m7 96. 5
5 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. cumbica-guarulhos-sp, brasil tel: 011-6465-6810 fax: 011-6465-6829 j98. 2
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7 preface this manual describes a usb host controller that complies with the open host controller interface specification release 1.0 and openhci legacy support interface specification release version 1.01 . read this manual thoroughly to help ensure smooth system design. also, be sure to observe the various notes in this manual (general notes, caution points, and restrictions). operation faults and a reduction in the quality and performance levels of lsi products may occur if these notes are not observed.
8 before starting a design, contact your local nec sales representative or distributor to make sure you have the most recent documentation.
9 contents chapter 1 features .......................................................................................................... ............ 15 1.1 features .................................................................................................................... ............................ 15 1.2 block diagram ............................................................................................................... ....................... 17 1.3 pin configuration ........................................................................................................... ...................... 18 1.4 pin configuration diagram................................................................................................... ............... 19 1.5 pin names and pin numbers ................................................................................................... ........... 20 chapter 2 pin functions.................................................................................................... ......... 21 2.1 pin table ................................................................................................................... ............................ 21 2.2 description of pin functions ................................................................................................ .............. 23 2.3 handling unused pins ........................................................................................................ ................. 26 chapter 3 description of usb host controller functions .................................. 27 3.1 overview of usb ............................................................................................................. ..................... 27 3.2 host controllers communication method ...................................................................................... .. 30 3.3 endpoint descriptor......................................................................................................... .................... 33 3.3.1 endpoint descriptor format ............................................................................................. ............. 33 3.3.2 endpoint descriptor field definitions .................................................................................. .......... 34 3.4 transfer descriptors ........................................................................................................ .................... 35 3.4.1 general transfer descriptor format ..................................................................................... ......... 35 3.4.2 general transfer descriptor field definitions.......................................................................... ....... 36 3.4.3 isochronous transfer descriptor format ................................................................................. ...... 37 3.4.4 isochronous transfer descriptor field definitions...................................................................... .... 38 3.5 host controller communications area ......................................................................................... ..... 39 3.5.1 host controller communications area format............................................................................. .. 39 3.5.2 host controller communications area description ....................................................................... 3 9 3.6 hc mode changes............................................................................................................. ................... 40 3.7 list service flow........................................................................................................... ....................... 41 3.8 legacy operations........................................................................................................... .................... 45 chapter 4 power management................................................................................................ 5 1 4.1 overview of power management ................................................................................................ ........ 51 4.2 bus states and device states ................................................................................................ ............. 52 4.3 transition conditions for bus states and device states ................................................................. 53 4.4 device state transition flow ................................................................................................ .............. 55 chapter 5 register information............................................................................................ 5 9 5.1 pci configuration space ..................................................................................................... ................ 59 5.2 operational registers ....................................................................................................... ................... 64 5.2.1 overview of operational registers...................................................................................... .......... 65
10 5.2.2 overview of legacy support registers ................................................................................... ....... 74 chapter 6 electrical characteristics............................................................................... 77 6.1 buffer list ................................................................................................................. ............................ 77 6.2 absolute maximum ratings .................................................................................................... ............ 78 6.3 recommended operating conditions ............................................................................................ .... 78 6.4 pin capacitance............................................................................................................. ....................... 78 6.5 dc characteristics (v dd = 3.0 v to 3.6 v, t a = 0 to +70 c) ................................................................ 79 6.6 power consumption........................................................................................................... .................. 83 6.7 system clock ratings........................................................................................................ .................. 83 6.8 ac characteristics (v dd = 3.0 v to 3.6 v, t a = 0 to +70 c) ................................................................ 84 chapter 7 timing charts .................................................................................................... ........ 87 7.1 pci clock................................................................................................................... ............................ 87 7.2 pci reset................................................................................................................... ............................ 87 7.3 pci output timing ........................................................................................................... ..................... 88 7.4 pci input timing ............................................................................................................ ....................... 88 7.5 pci clock reset ............................................................................................................. ....................... 88 7.6 crun vs. gnt................................................................................................................ ....................... 89 7.7 usb device disconnect detection............................................................................................. ......... 89 7.8 usb full speed device connect detection ..................................................................................... .. 89 7.9 usb low speed device connect detection...................................................................................... .90 7.10 usb signal rise/fall timing................................................................................................ ................ 90 7.11 usb differential signal .................................................................................................... .................... 90 7.12 usb eop signal............................................................................................................. ....................... 91 7.13 usb differential receiver allowable jitter................................................................................. ........ 91 chapter 8 usb host controller use method ................................................................ 93 8.1 usb host controller peripheral circuit example .............................................................................. 93
11 list of figures (1/2) figure no. title page 1-1 block diagram ............................................................................................................... ......................... 17 1-2 pin configuration ........................................................................................................... ......................... 18 1-3 pin configuration diagram................................................................................................... ................... 19 3-1 bus topology................................................................................................................ .......................... 27 3-2 full speed device cable and resistor connections ............................................................................ .. 28 3-3 low speed device cable and resistor connections ............................................................................. 28 3-4 relation between eds and tds................................................................................................ .............. 30 3-5 interrupt ed list........................................................................................................... ........................... 31 3-6 allocation of bandwidth ..................................................................................................... ..................... 31 3-7 when control/bulk service ratio is 4:1...................................................................................... ............ 32 3-8 endpoint descriptor format.................................................................................................. .................. 33 3-9 general td format........................................................................................................... ...................... 35 3-10 current buffer pointer/buffer end and 4-k boundary......................................................................... .... 37 3-11 isochronous td format ...................................................................................................... .................... 37 3-12 hc mode changes ............................................................................................................ ..................... 40 3-13 list service flowchart ..................................................................................................... ....................... 41 3-14 ed service flowchart ....................................................................................................... ...................... 42 3-15 td service flowchart ....................................................................................................... ...................... 43 3-16 done queue operations...................................................................................................... ................... 44 3-17 input-related legacy operation flowchart................................................................................... ........... 45 3-18 input emulation flowchart for usb keyboard/mouse ........................................................................... .46 3-19 combination of usb keyboard/mouse and legacy keyboard/mouse (input emulation) ....................... 47 3-20 output-related legacy operation flowchart.................................................................................. ......... 48 3-21 distinctions between legacy and usb........................................................................................ ........... 49 5-1 openhcis pci configuration space........................................................................................... ........... 63 6-1 v o vs. i o (pci buffer) .................................................................................................................. ............ 80 6-2 v cm (common mode voltage) vs. v di (differential input sensitivity) ...................................................... 82 7-1 pci clock waveforms......................................................................................................... .................... 87 7-2 pci reset waveforms ......................................................................................................... ................... 87 7-3 pci output timing ........................................................................................................... ....................... 88 7-4 pci input timing ............................................................................................................ ......................... 88 7-5 pci clock reset ............................................................................................................. ........................ 88 7-6 crun vs. gnt ................................................................................................................ ....................... 89 7-7 usb device disconnect detection ............................................................................................. ............ 89 7-8 usb full speed device connect detection..................................................................................... ....... 89 7-9 usb low speed device connect detection...................................................................................... ..... 90 7-10 usb signal rise/fall timing................................................................................................ ................... 90 7-11 usb differential signal .................................................................................................... ....................... 90 7-12 usb eop signal............................................................................................................. ........................ 91 7-13 usb differential receiver allowable jitter capacitance..................................................................... .... 91
12 list of figures (2/2) figure no. title page 8-1 circuit example of usb interface block...................................................................................... ........... 93 8-2 circuit example of legacy interface block ................................................................................... ......... 94
13 list of tables table no. title page 1-1 pin numbers ................................................................................................................. .......................... 20 2-1 pin table ................................................................................................................... ............................. 21 3-1 description of endpoint descriptors ......................................................................................... .............. 34 3-2 description of general td ................................................................................................... ................... 36 3-3 description of isochronous td ............................................................................................... ................ 38 3-4 description of host controller communications area .......................................................................... .. 39 3-5 gatea20 sequences........................................................................................................... .................... 49 4-1 device state transition conditions .......................................................................................... .............. 53 4-2 usb state transition conditions ............................................................................................. ............... 53 4-3 mutual relation between device state and pci or usb ........................................................................ 5 4 4-4 state control............................................................................................................... ............................ 55 5-1 pci configuration space ..................................................................................................... ................... 59 5-2 register information ........................................................................................................ ....................... 60 5-3 command register information................................................................................................ .............. 60 5-4 status register information ................................................................................................. ................... 61 5-5 base address (bar_ohci) register information ................................................................................ .. 61 5-6 i/o address register (pc/at) information .................................................................................... ......... 62 5-7 power management control/status information ................................................................................. .... 62 5-8 host controller operational registers ....................................................................................... ............. 64 5-9 legacy support registers .................................................................................................... .................. 64 6-1 absolute maximum ratings .................................................................................................... ................ 78 6-2 recommended operating conditions............................................................................................ ......... 78 6-3 pin capacitance ............................................................................................................. ........................ 78 6-4 dc characteristics.......................................................................................................... ........................ 79 6-5 dc characteristics (pci interface block).................................................................................... ............ 79 6-6 dc characteristics (usb interface block) .................................................................................... .......... 82 6-7 dc characteristics (control pin block)...................................................................................... ............. 83 6-8 power consumption characteristics........................................................................................... ............ 83 6-9 system clock ratings........................................................................................................ ..................... 83 6-10 ac characteristics (pci interface block)................................................................................... ............. 84 6-11 ac characteristics (usb interface block) ................................................................................... ........... 86 8-1 jumper settings............................................................................................................. ......................... 94
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15 chapter 1 features 1.1 features (1) functions ? complies with openhci specification release 1.0 and openhci legacy support interface specification release version 1.01 . ? supports asynchronous communication between host cpu and usb devices. ? supports two types of usb devices: full speed (12 mbps) devices and low speed (1.5 mbps) devices. ? system clock: 48 mhz (2) interface ? usb interface transceiver complies with universal serial bus specification revision 1.0 . switchable between full speed (12 mbps) and low speed (1.5 mbps) modes. ? pci interface buffer complies with pci local bus specification revision 2.1 and pci mobile design guide revision 1.0 . supports 32-bit, 33-mhz, 5-vpci/3.3-vpci operation. (3) communication with host cpu ? communicates via operational registers built into usb host controller ? communicates via the host controller communication area in the system memory space (4) memory and i/o space ? maps to 4-kbyte space within the 4-gbyte system memory space. ? 256-byte host controller communication area is allocated in the system memory space. ? the legacy support register is allocated to 60h/64h in the i/o space. (5) legacy support ? usb keyboard + usb mouse, usb keyboard + legacy mouse ? legacy keyboard + usb mouse, legacy keyboard + legacy mouse (6) on-chip fifo ?pci side read: 16 bytes (4 4 dwords), write: 16 bytes (4 4 dwords) ? usb side 64 bytes (64 1 byte) (7) root hub ? equipped with two downstream ports
chapter 1 features 16 (8) low power consumption ? on-chip clock run function ? on-chip pci clock stop/usb clock stop functions (9) others ? cmos process ? 3-v single power supply
chapter 1 features 17 1.2 block diagram figure 1-1. block diagram pci i/f operational register rd fifo wr fifo list process engine data fifo serial interface engine sequence control main control root hub transceiver transceiver pci-bus usb device usb device
chapter 1 features 18 1.3 pin configuration figure 1-2. pin configuration ad (31:00) cbe (3:0) par frame irdy trdy stop idsel devsel req gnt perr serr inta pclk rst crun sclk rcvbe smi wake dp (2:1) dn (2:1) oci (2:1) ppon (2:1) test (3:1) tmn (7:1) at legc iri1 iri2 iro1 iro2 a20s pci interface legacy interface (32) (4) (2) (2) (2) (2) (7) gnd +3.3 v v dd 3 (3) system interface usb interface test pins system clock buffer enable
chapter 1 features 19 1.4 pin configuration diagram figure 1-3. pin configuration diagram 12345678910111213141516171819202122232425 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 v dd legc rcvbe iri2 iri1 smi tmn1 wake test1 test2 test3 tmn2 gnd tmn3 tmn4 tmn5 ppon2 oci2 dn2 dp2 ppon1 oci1 dn1 dp1 v dd gnd sclk v dd tmn6 tmn7 crun gnd ad00 ad01 ad02 ad03 ad04 gnd ad05 ad06 ad07 cbe0 ad08 v dd ad09 ad10 ad11 ad12 ad13 gnd gnd pclk v dd at ir01 ir02 a20s gnd inta rst gnt req gnd ad31 ad30 ad29 ad28 ad27 v dd ad26 ad25 ad24 cbe3 idsel gnd v dd ad23 ad22 ad21 ad20 ad19 gnd ad18 ad17 ad16 cbe2 frame v dd irdy trdy devsel stop perr gnd serr par cbe1 ad15 ad14 v dd
chapter 1 features 20 1.5 pin names and pin numbers ad (31:00) : pci address and data smi : system management interrupt cbe (3:0) : pci bus command and byte enable dp (2:1) : usb d+ par : pci parity dn (2:1) : usb d - frame : pci cycle frame oci (2:1) : over current interrupt irdy : pci initiator ready ppon (2:1) : port power on trdy : pci target ready sclk : system clock stop : pci stop rcvbe : usb receiver and input buffer enable idsel : pci initialization device select at : at mode enable devsel : pci device select legc : legacy support enable req : pci request iri1 : irq1 input gnt : pci grant iri2 : irq12 input perr : pci parity error iro1 : irq1 output serr : pci system error iro2 : irq12 output inta : pci interrupt a20s : gatea20 state pclk : pci clock wake : wakeup interrupt rst : pci reset test (3:1) : test control crun : pci clock running tmn (7:1) : test signal table 1-1. pin numbers pin number pin name pin number pin name pin number pin name pin number pin name 1v dd 26 gnd 51 v dd 76 gnd 2 ad23 27 ad13 52 dp1 77 pclk 3 ad22 28 ad12 53 dn1 78 v dd 4 ad21 29 ad11 54 oci1 79 at 5 ad20 30 ad10 55 ppon1 80 iro1 6 ad19 31 ad09 56 dp2 81 iro2 7gnd 32v dd 57 dn2 82 a20s 8 ad18 33 ad08 58 oci2 83 gnd 9 ad17 34 cbe0 59 ppon2 84 inta 10 ad16 35 ad07 60 tmn5 85 rst 11 cbe2 36 ad06 61 tmn4 86 gnt 12frame 37ad05 62tmn3 87req 13 v dd 38 gnd 63 gnd 88 gnd 14 irdy 39 ad04 64 tmn2 89 ad31 15 trdy 40 ad03 65 test3 90 ad30 16 devsel 41 ad02 66 test2 91 ad29 17 stop 42 ad01 67 test1 92 ad28 18 perr 43 ad00 68 wake 93 ad27 19 gnd 44 gnd 69 tmn1 94 v dd 20 serr 45 crun 70 smi 95 ad26 21 par 46 tmn7 71 iri1 96 ad25 22 cbe1 47 tmn6 72 iri2 97 ad24 23 ad15 48 v dd 73 rcvbe 98 cbe3 24 ad14 49 sclk 74 legc 99 idsel 25 v dd 50 gnd 75 v dd 100 gnd
21 chapter 2 pin functions 2.1 pin table table 2-1. pin table pin name i/o buffer type active level function ad (31 : 0) i/o 5 v pci i/o pci ad [31 : 0] signal cbe (3 : 0) i/o 5 v pci i/o pci c/be [3 : 0] signal par i/o 5 v pci i/o pci par signal frame i/o 5 v pci i/o pci frame# signal irdy i/o 5 v pci i/o pci irdy# signal trdy i/o 5 v pci i/o pci trdy# signal stop i/o 5 v pci i/o pci stop# signal idsel i 5 v pci input pci idsel signal devsel i/o 5 v pci i/o pci devsel# signal req o 5 v pci output pci req# signal gnt i 5 v pci input pci gnt# signal perr i/o 5 v pci i/o pci perr# signal serr o 5 v pci n-ch open drain pci serr# signal inta o 5 v pci n-ch open drain low pci inta# signal pclk i 5 v pci input pci clk signal rst i 5 v schmitt input low pci rst# signal crun i/o 5 v pci i/o (n-ch open drain) pci clkrun# signal sclk i 5 v schmitt input system clock input smi o 5 v i ol = 12 ma n-ch open drain low system management interrupt output dp (2 : 1) i/o usb d+i/o usbs d+ signal dn (2 : 1) i/o usb d - i/o usb?s d - signal oci (2 : 1) i (i/o) 5 v input with excessive through current prevention function high usb root hub port?s overcurrent status input ppon (2 : 1) o 5 v i ol = 6 ma output high usb root hub port?s power supply control output rcvbe i 5 v input high usb receiver and input buffer enable signal at i (i/o) 5 v schmitt input high legacy support switch legc i (i/o) 5 v schmitt input high legacy support switch iri1 i (i/o) 5 v input with excessive through current prevention function high int input from keyboard iri2 i (i/o) 5 v input with excessive through current prevention function high int input from mouse iro1 o 5 v i ol = 6 ma n-ch open drain high int output from keyboard iro2 o (i/o) 5 v i ol = 6 ma n-ch open drain high int output from mouse a20s o (i/o) 5 v i ol = 6 ma n-ch open drain gatea20 state output wake o 5 v i ol = 6 ma output high wakeup interrupt output test (3 : 1) i 3 v input with 50 k w pull up r test pin tmn (7 : 1) i/o 3 v i/o with 50 k w pull up r test pin
chapter 2 pin functions 22 remarks 1. the 5-v buffer in the table indicates a 5-v tolerant buffer. 5-v tolerant means that the buffer is a 3- v buffer with 5-v maximum voltage. 2. 5 v pci indicates a pci buffer that has a 5-v maximum voltage circuit which complies with the 3-v pci standard. it does not indicate a buffer that fully complies with the 5-v pci standard. however, this function can be used for evaluating the operation of a device by attaching a 5-v add-in card beforehand. 3. the signals marked as (i/o) in the above table operate as i/o signals during testing. however, they do not need to be considered in normal use situations.
chapter 2 pin functions 23 2.2 description of pin functions ? power supply pin pin no. direction function v dd 1, 13, 25, 32, 48, 51, 75, 78, 94 - +3 v power supply gnd 7, 19, 26, 38, 44, 50, 63, 76, 83, 88, 100 - ground ? pci interface pin pin no. direction function ad (31 : 00) 2 to 6, 8 to 10, 23, 24, 27 to 31, 33, 35 to 37, 39 to 43, 89 to 93, 95 to 97 i/o pci ad [31 : 00] signal cbe (3 : 0) 11, 22, 34, 98 i/o pci c/be [3 : 0] signal par 21 i/o pci par signal frame 12 i/o pci frame# signal irdy 14 i/o pci irdy# signal trdy 15 i/o pci trdy# signal stop 17 i/o pci stop# signal idsel 99 i pci idsel signal devsel 16 i/o pci devsel# signal req 87 o pci req# signal gnt 86 i pci gnt# signal perr 18 i/o pci perr# signal serr 20 o pci serr# signal inta 84 o pci inta# signal pclk 77 i pci clk signal rst 85 i pci rst# signal crun 45 i/o pci clkrun# signal remark for details of pci operations, see the pci local bus specification revision 2.1 . ? system clock pin pin no. direction caution sclk 49 i system clock input apply 48-mhz clock input. ? test pins pin pin no. direction caution test (3 : 1) 65, 66, 67 i be sure to leave open on circuit board. tmn (7 : 1) 46, 47, 60, 61, 62, 64, 69 i/o be sure to leave open on circuit board.
chapter 2 pin functions 24 ? system interface pin pin no. direction function smi 70 o system management interrupt output changed to inta by ownership change before being output. 0: interrupt occurs 1: interrupt does not occur rcvbe 73 i usb receiver/input buffer enable signal 0: excessive through current prevention/differential buffer operating current cut-off function on 1: excessive through current prevention/differential buffer operating current cut-off function off the pins being controlled are as follows. dp (2 : 1), dn (2 : 1), oci (2 : 1), iri1, iri2 wake 68 o wakeup request signal is output from the usb. 0: no wakeup request 1: wakeup request exists ? usb interface pin pin no. direction function dp (2 : 1) 52, 56 i/o usbs d+ signal shared with dnx pins having the same numbers. dn (2 : 1) 53, 57 i/o usbs d - signal shared with dpx pins having the same numbers. oci (2 : 1) 54, 58 i pin for inputting the overcurrent status of the usb root hub port 0: no power supply problem 1: overcurrent has occurred ppon (2 : 1) 55, 59 o power supply control output for usb root hub port 0: power supply off 1: power supply on
chapter 2 pin functions 25 ? legacy support interface pin pin no. direction function at 79 i legacy support 0: legacy off 1: legacy on legc 74 i legacy support switch 0: legacy off 1: legacy on when off, l clamp iri1 and iri2 and leave iro1, iro2, and a20s open. iri1 note 71 i int input from keyboard: active h iri2 note 72 i int input from mouse: active h iro1 80 o int output from keyboard: active h iro2 81 o int output from mouse: active h a20s 82 o gatea20 state output note irq is sampled using the 12-mhz clock signal generated by sclk, and an interrupt is detected as a result. the next irq is not received during emulation. after emulation is completed, an interrupt can be received once the irq's h level has been sampled.
chapter 2 pin functions 26 2.3 handling unused pins handle unused pins as shown below. pin direction connection method dpx i/o connect via 15 k w 5% pull-down resistor. dnx i/o connect via 15 k w 5% pull-down resistor. ocix i ?l? clamp pponx o no connection (open) test (3 : 1) i no connection (open) tmn (1 : 7) i/o no connection (open) when the legacy function is off (at = l, legc = l), handle unused pins as shown below. pin direction connection method iri1 i ?l? clamp iri2 i ?l? clamp iro1 o no connection (open) iro2 o no connection (open) a20s o no connection (open)
27 chapter 3 description of usb host controller functions this chapter provides an overview of the usb, the operations of the host controller, and the structure of the interface data that is used. for details, see the open host controller interface specification release 1.0 and openhci legacy support interface specification release version 1.01 . 3.1 overview of usb the usb (universal serial bus) is a type of serial bus that enables transfer of data between a host computer and various types of peripheral devices. the usb host has point-to-point connections with usb devices via a tiered star topology, in which each star contains a device called a hub. figure 3-1 shows a usb bus topology. the usb enables connection of up to 127 devices via this tiered star topology. in addition, devices can be connected or disconnected while the system is still operating. figure 3-1. bus topology host roothub hub 1 hub 2 hub 4 hub 3 node node node node node node node host (root tier) tier 1 tier 2 tier 3 tier 4 usb signals are transferred point-to-point as differential signals using two signal lines. there are two signal trace modes: full speed mode (12 mbs) and low speed mode (1.5 mbs). low speed mode is used in low-cost devices such as mouse devices that do not require much emi protection. as shown in figures 3-2 and 3-3, the mode is set as full speed or low speed based on the position of the terminating resistors connected to both ends of the usb cable. terminating resistors are also used at each port to detect when devices are being connected or disconnected.
chapter 3 description of usb host controller functions 28 figure 3-2. full speed device cable and resistor connections r 1 d + d d + d r 1 r 2 f.s./l.s.usb transceiver twisted pair shielded host or hub port 5 meters max. z 0 = 90 w 15 % r 1 =15 k w r 2 =1.5 k w f.s. usb transceiver hub upstream port or full speed function figure 3-3. low speed device cable and resistor connections r 1 d + d d + d r 1 r 2 f.s./l.s.usb transceiver untwisted, unshielded host or hub port 3 meters max. r 1 = 15 k w r 2 = 1.5 k w l.s. usb transceiver low speed function the host schedules and manages data transfers. consequently, transfers must always be started by the host, and all transfers are performed using up to three packets (token, data, and handshake packets). the token packet sends usb devices information on the processing direction, type of transaction, address, endpoint, etc. the usb device decodes the address field and determines whether or not it has been accessed. the data packet contains the data that is sent in the direction (from host to device or from device to host) that is specified by the token packet. the handshake packet is returned to the source of the transfer to indicate whether or not the transfer was successful. the following four types of transfers occur between usb hosts and usb devices. ? interrupt transfer this is a small data transfer which is used to send information from a usb device to client software. the hcd (host controller driver) sends a token packet to a device within the period required by the device, after which the usb data transfer is executed. ? isochronous transfer this is a periodic data transfer that uses a constant data transfer rate. ? control transfer this is a non-periodic data transfer that is used to send information about configuration, commands, and status between the client software and a usb device. ? bulk transfer this is a non-periodic data transfer that is used to send large amounts of information between the client software and a usb device.
chapter 3 description of usb host controller functions 29 under openhci, data transfers are divided into two categories: periodic and non-periodic. periodic transfers, which are executed within a specified period, are further divided into the interrupt and isochronous transfer types. non-periodic transfers, which are not executed periodically, are divided into control and bulk transfer types. to implement the following types of operations, a device called a usb host controller and software called the usb hcd must both be installed on the host computer. openhci is the specifications that apply to the relation between the host controller and the hcd software. this device complies with the open hci specification release 1.0 and openhci legacy support interface specification release version 1.01 .
chapter 3 description of usb host controller functions 30 3.2 host controllers communication method the host controller (hc) and the host controller driver (hcd) communicate via the following two paths. ? operational registers ? host controller communications area (hcca) in communication that uses the operational registers which are built into the hc, the hc is the pci target device. the operational registers are a set of registers that include control bits, status bits, list pointers, etc. they also include pointers that indicate the position of the hcca (host controller communications area) within system memory. the hc becomes the pci bus master for communications that are executed via the hcca. the hcca is a 256-byte system memory area that contains head pointers to the interrupt ed list, head pointers to the done queue, and frame-related status information. the software uses this system memory to directly control the hcs functions without reading from the hc, as long as operation conditions are normal (i.e., there are no errors). these two paths are used for handling hc control tasks and usb data transfer results. the hcd executes communication between the hc and usb devices, based on the enqueued ed (endpoint descriptor) and td (transfer descriptor). an ed contains information (maximum packet size, endpoint address, endpoint speed and data flow direction) that the hc requires to communicate with the endpoint, and the ed can also be used as the td queues anchor. the hcd generates eds and assigns them to the various endpoints, when are then listed and linked. a td contains information (data toggle information, buffer positions in system memory, and complete status code) that is required for the data packet to be sent. each td also contains information (data buffer size ranging from 0 to 8192 bytes, with a maximum of 1024-byte transfer per data packet) that is related to at least one data packet. enqueued tds are serviced in fifo order. the td queue is linked with a certain endpoints ed and the tds are linked with the td queue. the hcd generates data from this structure and passes the data to the hc for processing. figure 3-4 shows the relation between eds and tds. figure 3-4. relation between eds and tds head ptr ed ed ed ed td td td td td td td ed lists are categorized into four types: bulk, control, interrupt, and isochronous. three types of head pointers of ed list are held (one for each of the above types except isochronous). the isochronous ed list is simply linked following the interrupt ed. the head pointers to the bulk and control ed lists are held in the operational registers, while the head pointers to the interrupt ed list are held in the hcca. there are 32 interrupt head pointers, and the head pointer that is used by a frame is determined based on the usage of the frame counter?s low-order 5 bits (indicating the addresses of the 32 types). the interrupt ed list structure is a tree structure, as is shown in figure 3- 5, in which the execution interval is determined according to the depth of the points where several paths intersect. in other words, interrupt eds that are linked to the root of the tree structure are allocated and executed at a rate of 1 ms per ed.
chapter 3 description of usb host controller functions 31 figure 3-5. interrupt ed list 0 16 8 24 4 20 12 28 2 18 10 26 6 22 14 30 1 17 9 25 5 21 13 29 3 19 11 27 7 23 15 31 32 16 8 4 2 1 interrupt head pointers endpoint poll interval (ms) interrupt endpoint descriptor placeholder figure 3-6 shows how the openhci?s bandwidth is allocated. the hc selects the list to be serviced based on a prioritization algorithm. control and bulk lists take priority from the start of the frame to the point where hcfmremaining becomes hcperiodicstart. when hcfmremaining becomes hcperiodicstart, periodic list servicing takes priority. the priority of periodic list servicing is higher than that of control or bulk servicing up until the point where periodic list servicing is completed or the frame period is completed. after periodic list servicing is completed, control or bulk list servicing is resumed. figure 3-6. allocation of bandwidth sof time np periodic np 1.0 ms interrupt/isochronous list servicing begins with servicing the interrupt ed head pointer that is serviced for the current frame. since isochronous lists are attached after interrupt lists, interrupt lists must have a higher priority than isochronous lists. bulk and control list servicing resumes at the point in each list where servicing was interrupted. when servicing reaches the end of the list, a value is loaded from the head pointer and servicing continues. the control endpoint is given access privileges that are at least equivalent to those of the bulk endpoint, and this service ratio is determined by controlbulkserviceratio in hccontrol. figure 3-7 shows an example where the control/bulk service ratio is 4:1. when control and bulk take priority, the hc executes ed servicing of each list according to the controlbulkserviceratio.
chapter 3 description of usb host controller functions 32 figure 3-7. when control/bulk service ratio is 4:1 ctrl ed ctrl ed ctrl ed ctrl ed bulk ed this control/bulk service ratio is retained over several frames. as soon as the hc services the data packet for one of the tds included in an ed, it begins servicing the next ed.
chapter 3 description of usb host controller functions 33 3.3 endpoint descriptor an ed is always allocated in 16-byte units to system memory. when the ed list is referenced, if it contains a td that is linked to an ed, the hc executes the transfer specified by that td. if the hcd must change the head pointer (headp) value, list servicing for all eds that have the same transfer type as the ed to be deleted must be rendered invalid so as to prevent the hc from accessing the eds. therefore, the hcd sets a skip bit. 3.3.1 endpoint descriptor format figure 3-8. endpoint descriptor format ch 0 3 1 2 6 0 0 dword 0 dword 1 dword 2 dword 3 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 ?s en fa mps f d td queue tail pointer (tailp) td queue head pointer (headp) next endpoint descriptor (nexted)
chapter 3 description of usb host controller functions 34 3.3.2 endpoint descriptor field definitions table 3-1. description of endpoint descriptors name hc access description fa r function address usb address of function that includes the endpoint that is controlled by this ed en r endpoint number endpoint address in function direction indicates the data flow direction (in or out). if neither in nor out are specified, the transfer direction is defined by the tds pid (packet id) field. code direction 00b get direction from td 01b out 10b in 11b get direction from td dr s r speed this indicates the endpoints speed. ? full-speed (s = 0) ? low-speed (s = 1) krskip when this bit is set, the hc proceeds to the next ed without accessing the td queue or issuing a usb token to the endpoint. frformat this indicates the format of a td that is linked to this ed. for control, bulk, or interrupt endpoints, if f = 0, then the general td format is used. for isochronous endpoints, if f = 1, the isochronous td format is used. mps r maximum packet size this field indicates the maximum number of bytes (1024 bytes) per data packet that can be received from the endpoint or sent to an endpoint. when a write operation (out or setup) is executed from the hc to the endpoint, the size of the data packet to be sent always becomes either the maximum packet size or the size of the data in the buffer, whichever is smaller. when a read operation (in) is executed from the endpoint to the hc, the data packet size is determined according to the endpoint. tailp r td queue tail pointer when tailp and headp have the same value, the list does not contain any tds that can be serviced by the hc. when the tailp and headp values are different, the list contains tds. hr/whalted this bit is set by the hc to indicate when servicing of the endpoint td queue has been suspended due to a normal td servicing error. c r/w toggle carry this bit is the data toggle carry bit. when a td is retired, the final data toggle value (lsb in the data toggle field) that was used by the retired td is written. this field cannot be used by isochronous endpoints. headp r/w td queue head pointer this indicates the next td to be serviced at this endpoint. nexted r next ed when its value is other than zero, this bit indicates the next ed.
chapter 3 description of usb host controller functions 35 3.4 transfer descriptors tds (transfer descriptors) are used by the hc to indicate the buffer for the data that is sent to or from an endpoint. tds are divided into two types: general tds and isochronous tds. general tds are used by interrupt, control, and bulk endpoints while isochronous tds are used for handling isochronous transfers. for both general and isochronous tds, buffers ranging from 0 bytes to 8,192 bytes can be indicated. also, the data buffer described by one td can be divided into two pages. this enables the elimination of various problems, such as problems related to forced physical connection of buffers or transfer of surplus data. when the hcd appends a td, the td indicated by tailp is linked to the new td, and tailp is then changed to indicate the appended td. therefore, the appended td is always added to the end of the td queue. the hc services the td asynchronously in relation to servicing performed by the host processor. consequently, when it is necessary to switch from the td queue to something else, the hcs endpoint td queue servicing must be suspended to avoid problems from occurring due to this switch. suspension of td servicing is achieved when the hcd sets the skip bit in the ed to be deleted. 3.4.1 general transfer descriptor format general tds are used for control, bulk, or interrupt transfers, and they must always be allocated in 16-byte units to system memory. figure 3-9. general td format 0 3 1 2 8 0 0 dword 0 dword 1 dword 2 dword 3 2 7 2 6 2 5 2 4 2 3 2 1 2 0 1 9 1 8 0 3 cc r ec t di dp current buffer pointer (cbp) next td (nexttd) buffer end (be)
chapter 3 description of usb host controller functions 36 3.4.2 general transfer descriptor field definitions table 3-2. description of general td name hc access description r r buffer rounding when this bits value is 0, the data buffer defined by the last data packet sent from the endpoint specified by the td must be a completely full buffer. when its value is 1, the data buffer defined by the last data packet is not full, even if there are no errors. direction/pid this indicates the data flow direction and pid used by a token. this field only has significance in relation to the hc when 00b or 11b is set to indicate that the eds d field has delayed the pid judgment until the td. code pid type data direction 00b setup to endpoint 01b out to endpoint 10b in from endpoint 11b reserved dp r di r delay interrupt this indicates the time until a interrupt occurs as notification of completed td servicing. when the td has been completed, the hc delays the interrupt event until the frame indicated by this bit. when this bits value is 111b, interrupts related to completion of this td do not occur. t r/w data toggle this field is used to generate a comparison or occurrence of data pid values (data0 or data1). this field is updated after each successful transfer of a data packet. when the data toggle fields msb is 0, the data toggle fields lsb, which was acquired from the eds toggle carry bit, is ignored. when data toggle fields msb is 1, the data toggle fields lsb indicates the data toggle. ec r/w error count this field is incremented after each transmission error. if an error occurs after the error count has reached 2, the type of error is written to the condition code field and is transferred to the done queue. if servicing ends without any errors, the error count is reset to 0. cc r/w condition code this field is updated each time processing is executed, regardless of whether or not the processing was successful. if it was successful, this field is set as n o e rror . if unsuccessful, it is set according to the type of error. cbp r/w current buffer pointer this includes the next physical address in memory that will be accessed by a transfer from or to an endpoint. a 0 value indicates either that the data packet has zero length or that all bytes have been transferred. nexttd r/w next td this specifies the next td in the td list linked to the endpoint. be r buffer end this indicates the physical address of the last byte in the tds buffer.
chapter 3 description of usb host controller functions 37 the general tds current buffer pointer indicates the data buffer address used for a data packet transfer to or from an endpoint. if the transfer is completed without the occurrence of any kind of error, the hc advances the current buffer pointer by exactly the number of transferred bytes. if the buffer address indicated by the current buffer pointer exceeds the 4-k boundary during a data packet transfer, the high-order 20 bits of the buffer end field is copied to the working value from the current buffer pointer. the next buffer address becomes byte 0 in the same 4-k page space that is used when the final byte is retained. figure 3-10. current buffer pointer/buffer end and 4-k boundary 1 data packet current buffer pointer 4 k boundary 4 k boundary buffer end 4 k boundary 4 k 3.4.3 isochronous transfer descriptor format isochronous tds are used only by isochronous endpoints. all tds linked to the ed must use this format when f = 1. this td is allocated to system memory in 32-byte units. figure 3-11. isochronous td format 0 3 1 2 7 0 4 0 0 dword 0 dword 1 dword 2 dword 3 2 8 2 6 2 4 2 3 2 1 2 0 cc di 1 6 1 5 1 2 1 1 0 5 ?c sf offset1/psw1 offset3/psw3 offset5/psw5 offset7/psw7 offset0/psw0 offset2/psw2 offset4/psw4 offset6/psw6 buffer page 0 (bp0) nexttd buffer end (be) dword 4 dword 5 dword 6 dword 7
chapter 3 description of usb host controller functions 38 3.4.4 isochronous transfer descriptor field definitions table 3-3. description of isochronous td name hc access description sf r starting frame this includes the low-order 16 bits of the number of frames sent by the isochronous tds first data packet. di r delay interrupt this indicates the time until a interrupt occurs following completion of isochronous td servicing. fc r frame count this is the number of data packets indicated by the isochronous td. when frame count = 0, one data packet is included and when frame count = 7, eight data packets are included. cc r/w condition code this field includes a completion code when an isochronous td has been transferred to the done queue. bp0 r buffer page 0 this is the physical page number of the first byte in the data buffer used by the isochronous td. nexttd r/w next td this indicates the next isochronous td in the isochronous td queue linked to an ed. be r buffer end this includes the physical address of the buffers last byte. offsetn r offset this is used to determine the size and start address of an isochronous data packet. pswn w packet status word this includes the size of the completion code and the received isochronous data packet. isochronous tds have a (frame count + 1) frame buffer with a continuous range from 1 to 8. the first data packet is sent when the low-order 16 bits of hcfmnumber matches the isochronous tds starting frame value. if the buffer address exceeds the 4-k boundary during a data packet transfer, the high-order 20 bits of the buffer end field is used as the physical address of the next page. consequently, the next buffer address becomes byte 0 in the same 4-k page space that is used when the final byte is retained.
chapter 3 description of usb host controller functions 39 3.5 host controller communications area the hcca (host controller communications area) is a 256-byte area in system memory that is used by the system software for sending and receiving control/status information to and from the hc. the system software always writes the address of the area to the hcs hchcca field. 3.5.1 host controller communications area format table 3-4. description of host controller communications area offset size (bytes) name r/w description 0 128 hccalnterrupttable r this 32-dword entry table is a pointer to ed interrupt lists. 0 80 2 hccaframenumber w this includes the current frame number. this value is updated by the hc before periodic list servicing of the frame begins. 0 82 2 hccapad1 w when the hc updates the hccaframenumber value, the hc sets ?0? to this word. 0 84 4 hccadonehead w when the hc reaches the end of a frame and a decremented value of ?0? is shown as the delay interrupt value, the hc writes the current hcdonehead value to this field. at this point, interrupts occur as valid interrupts. the hc does not write again until the software clears the wd bit in the hcinterruptstatus register. if this field has a value of ?0?, interrupts can occur for reasons other than updating of hccadonehead, and the hcinterruptstatus register must be accessed to determine the cause of the interrupt. if this field?s value is not ?0?, the interrupt is due to updating of the done queue. if this field?s lsb is not ?0?, another interrupt event has occurred. the hcinterruptstatus field must be checked to determine the cause of that interrupt. 0 88 116 reserved r/w this field is reserved for use by the hc. 3.5.2 host controller communications area description hccainterrupttable is a 32-dword entry table which functions as a pointer to the ed lists various interrupt lists. the more of these lists that an ed is linked to, the higher the execution rate. the execution rate is 32 ms for an ed that is in only one list, but it is 6 ms for an ed that is in two lists. an ed that is linked to all 32 lists is executed at a rate of once per frame. the last entry in each of the 32 interrupt lists must specify an isochronous list. after an sof (start of frame) token is sent, the hc overwrites hccaframenumber using the framenumber value from hcfmnumber before it starting reading the ed to be serviced in a new frame.
chapter 3 description of usb host controller functions 40 3.6 hc mode changes hostcontrollerfunctionalstate indicates which of the four states (modes) the hc is in: u sb o perational , u sb r eset , u sb s uspend , and u sb r esume . the hcd can change usb modes only as shown in figure 3-12 and the hc can execute only one change: from u sb s uspend to u sb r esume during a remote wakeup event. figure 3-12. hc mode changes u sb o perational u sb s uspend u sb r esume u sb r eset u sb r eset write u sb o perational write u sb r eset write hardware reset u sb r eset write u sb s uspend write u sb o perational write software reset u sb r esume write or remote wakeup when in u sb o perational mode, the hc services lists and issues an sof token. frameinterval is loaded to frameremaining at the same time as the mode is being changed to u sb o perational . the first sof token to be sent after changing to u sb o perational mode is sent at the frame boundary when changing from frameremaining (value: ?0?) to frameinterval. at u sb r eset , the hc forcibly sends a reset signal to the bus. after a hardware reset, the hc always changes to u sb r eset mode. when in u sb s uspend mode, the usb is temporarily stopped. when in this mode, the hc monitors the usb wakeup operations. the hc can forcibly change to u sb r esume mode according to the remote wakeup condition. this change may conflict with the change to u sb r eset mode that is performed by the hcd. when such a conflict has occurred, the hcd?s change to u sb r eset mode takes priority. a change to u sb r esume mode is not possible during the first 5 ms following a change to u sb s uspend mode. when in u sb r esume mode, the hc forcibly sends a resume signal to the bus. while in u sb r esume mode, the root hub always passes a usb resume signal to downstream ports. the change to u sb r esume is started by a remote wakeup signal sent by the hcd or the root hub.
chapter 3 description of usb host controller functions 41 3.7 list service flow figure 3-13 shows a list service flowchart. after the hc determines which list to service, list servicing is executed via this list service flow pattern. since lists are periodically rendered invalid by the hcd due to ed switching (or other reasons), the hc must first check whether or not the target list is valid by checking each list enable bit in hccontrol when servicing the list. figure 3-13. list service flowchart read head pointer service endpoint descriptor set hc_currented = rc_headed set _filled = 0 bulk list? periodic list? control list? nexted = 0? head pointer = 0? isochronous ed? control/bulk ratio satisfied? isochronous ed? hc_currented = 0? _filled = 1? (bulk or control) list enabled? iso list enabled? hc_currented = 0? iso list enabled? finished finished finished service list finished yes yes yes yes yes yes yes yes yes yes yes yes yes yes no no no no no no no no no no no no no no
chapter 3 description of usb host controller functions 42 if the checked list is valid, the hc services the list. if it is invalid, the hc skips that list and proceeds to the next list. when a list is valid, the hc checks the position of the first ed for which servicing is requested. during periodic list servicing, if the head pointer value is 0, it means there are no eds in the list and the hc proceeds to the next list. by contrast, during non-periodic list servicing, if the currented value in each list is 0, the hc checks each listfilled value. if it finds that the listfilled value has been set to 1, it means that there is at least one ed in the target list that requires servicing. in such cases, the hc copies the headed value to currented and clears the filled bit to 0, then services the ed indicated by currented. if the hc finds a 0 value when checking listfilled, it proceeds to the next list. after servicing the ed, if the current list is a periodic list, the hc checks nexted in the just-completed ed then continues servicing the next ed. if it finds that the nexted value is 0, the hc proceeds to the non-periodic list. for bulk lists, the hc simply proceeds to the next list. for control lists, the next action varies depending on whether or not the number of control eds indicated by the control/bulk service ratio has been serviced. figure 3-14 shows an ed service flowchart. figure 3-14. ed service flowchart periodic list? headp = tailp? finished service endpoint descriptor service transfer descriptor set _filled = 1 (bulk or control) halt = 1 or skip = 1? no no no yes yes yes first, the hc reads the ed to be serviced from the system memory via the pci bus. next, the hc determines whether or not that ed actually needs to be serviced. if the ed?s skip bit or halted bit has a value of ?1?, the hc skips the ed and proceeds to the next ed or list. if the hc determines that the ed needs to be serviced, it next determines whether or not there are any tds that can be handled in a queue. the hc compares the ed?s tailp and headp values and, if the values match, it concludes that the list does not include any valid tds, so it proceeds to the next ed or list. if the tailp and headp values differ, the hc services the corresponding td. figure 3-15 shows a td service flowchart. when the hc services an isochronous td, it first calculates the relative frame number to determine whether or not a packet should be sent during the current frame. this relative frame number is used to select offset [r] and offset [r+1]. if the relative frame number matches the td?s framecount value, offset [r+1] (bufferend+1) is selected. the data buffer size for each transfer is calculated by subtracting offset [r] from offset [r+1], and the address is determined based on offset [r]. when bit 12 of offset [r] is ?0?, the isochronous td?s bufferpage0 is used as the high-order 20 bits of the address. when bit 12 of offset [r] is ?1?, the high-order 20 bits of bufferend are used as the high-order 20 bits of the address.
chapter 3 description of usb host controller functions 43 figure 3-15. td service flowchart read packet from memory execute usb transaction write packet to memory compare number with frame in ed calculate packet addr and size service transfer descriptor status writeback retire td perform sof check td complete? time available? time available? pid = out? frame-number > n? frame-number < 0? finished gtd itd yes (error) yes (early) no no yes no yes yes yes no no no (frame-number provides offset) execute usb transaction perform sof check when servicing a general td, the hc gets the next memory address from currentbufferpointer. when data is sent to or from the currentbufferpointer address, the data may be too large to fit onto one physical page and may therefore occupy several pages. in such cases, the high-order 20 bits of bufferend are used instead of the high- order 20 bits of currentbufferpointer as the address?s high-order 20 bits. the maximum amount of data that can be transferred between devices is their the ed?s maximumpacketsize value or the remaining buffer size, whichever is smaller. after determining the packet size, the hc must check whether or not it can send the packet before the end of the frame. if the value of the bit time request for the packet to be sent is greater than the frame?s remaining bit time value, the packet cannot be sent.
chapter 3 description of usb host controller functions 44 after servicing the general td, the hc updates four general td fields: conditioncode, datatoggle, errorcount, and currentbufferpointer. meanwhile, once isochronous td servicing is completed, the hc updates the offset [r] value to the packet status word. if the td is successfully serviced (all data is sent or received) or if an error has occurred, the hc moves the td to the done queue and updates the done queue interrupt counter. also, the hc updates the ed to change the values in the headp, togglecarry, and halted fields. in order to enqueue the td into the done queue, the hc first copies the current tds nexttd value to the eds headp field. next, it writes the hcdonehead value to the nexttd field of the td to be enqueued. finally, it writes the address of the td to be enqueued to the hcdonehead field (see figure 3-16). figure 3-16. done queue operations ed headp td nexttd td nexttd hcdonehead nexttd td nexttd td nexttd 1 3 2 at this point, the hc uses the td?s final data toggle value to update the ed?s togglecarry field. if the td is retired due to an error, the hc also updates the ed?s halted bit. after the above series of operations, the hc writes the hcdonehead value to the hcca and updates the done queue interrupt counter using the delay interrupt value (based on number of issued sof tokens), which defines the time until an interrupt is generated. however, this counter value is not updated if it is already greater than the delay interrupt value of td. the done queue interrupt counter is decremented after each sof token, and when the counter value reaches ?0?, the hc writes the current hcdonehead value to hccadonehead immediately at the boundary of the next frame. after the hcdonehead value has been written to the hcca, the hc resets the hcdonehead value to ?0? and sets ?1? to the writebackdonehead field in hcinterruptstatus, which triggers an interrupt. in this manner, the done queue is transferred from the hc to the hcd via the hcca. the hcd services the done queue and supplies notification of completion to the software that requested the transfer. while writebackdonehead is being set, the hc does not write the hcdonehead value to the hcca. if another done queue has been set up to be received from the hc, writebackdonehead is cleared by the hcd.
chapter 3 description of usb host controller functions 45 3.8 legacy operations this section describes legacy functions. legacy functions are provided to directly support the software belonging to an older (legacy) type of keyboard or mouse device by enabling data from usb keyboard or mouse devices to operate via a legacy keyboard or mouse device interface. these legacy functions are valid when the legc pin and at pin are both clamped to h. operations are defined for three conditions: when all connected keyboard/mouse devices are legacy devices, when all are usb devices, and when one or more of each type of device is connected. figure 3-17 shows an operational flowchart of input-related legacy functions. when the legacy functions are valid (enabled), the hc first checks hcecontrols emulationenable and externalirqen fields. if emulationenable has been set to 1, connected usb keyboard or mouse devices are emulated to operate like legacy keyboard or mouse devices (only usb keyboard or mouse devices are valid). if externalirqen has been set to 1, connected usb keyboard or mouse devices are emulated to operate like legacy keyboard or mouse devices, and compatibility of legacy keyboard/mouse operations is maintained (both usb and legacy keyboard or mouse devices are used). figure 3-17. input-related legacy operation flowchart i/o access to hc disable legacy support input emulation for usb keyboard/mouse externallrqen = 0? emulationenable = 1? externallrqen = 0? keyboard/mouse data from legacy products. emulation for legacy or usb keyboard/mouse interrupt through iro2 = iri2 yes yes yes no no no iro1 = iri1 note note even if iri1 is on, irq1active remains at l. similarly, even if iri2 is on, irq12active remains at l. when 0 is the value of both emulationenable and externalirqen, only legacy keyboard or mouse devices are valid, which means that irq1 (keyboard interrupt) and irq12 (mouse interrupt) are sent from the keyboard controller to the system directly via the hc. the hc does not receive i/o access (60h/64h), which is direct access to the keyboard controller, and does not perform any special processing. figure 3-18 shows an input emulation flowchart for usb keyboard or mouse devices. the hc always performs interrupt list service for each frame. when the transfer that is performed according to the td is completed, the td is linked to the done queue and a write operation to hccadonehead and the writebackdonehead interrupt occur after a specified amount of time (delay interrupt). if the correctly transferred data includes usb keyboard or mouse data, the system software sets 1 to characterpending in hcecontrol. the hc checks that command reg.s memory access field has been set to 1, hcestatuss outputfull field has been set to 0, hcestatuss characterpending field has been set to 1, and hcestatuss emulationenable field has been set to 1, after which an emulation interrupt occurs. the output destination for this interrupt is set via hccontrols interruptrouting field.
chapter 3 description of usb host controller functions 46 figure 3-18. input emulation flowchart for usb keyboard/mouse s oftware (hdc, bios, driver) proceed ir note 4 = 1:smi ? 0 ir note 4 = 1:inta ? 0 hceoutput ? usb date outputfull ? 1 keyboard date:auxoutputfull ? 0 mouse date:aux outputfull ? 1 aof note 6 = 0:iro1 ? 1 aof note 6 = 1:iro2 ? 1 ir note 4 = 1:smi ? 0 ir note 4 = 0:inta ? 0 i/o 60h access intercept ad ? hceoutput outputfull ? 0 iro1 ? 0, iro2 ? 0 emulation for usb keyboard/mouse i/o 60h read irqen = 1& outputfull = 1 finished emulation done finished ma note 1 = 1? & of note 2 = 0?& cp note 3 = 1? done queue process writebackdonehead interrupt no yes yes td for usb keyboard/mouse done without error notes 1. ma = pci command reg. memory access 2. of = outputfull 3. cp = characterpending (set by system software) 4. ir = interruptrouting 5. the writebackdonehead interrupt is generated at the same time as the emulation interrupt. the system software acknowledges these interrupts and must clear both of them. 6. aof = auxoutputfull when the system software detects the emulation interrupt, the transferred data is written to hceoutput reg. (108h) via a memory write operation and 1 is set to the outputfull field. in addition, 0 is set to hcestatuss auxoutputfull field if the data is keyboard data and 1 is set to that field if the data is mouse data. at that point, the system software performs operations such as deleting the contents of the tds donequeue field or canceling interrupts. this setting asserts iro1 (irq1) if for keyboard data or iro2 (irq12) if for mouse data. in cases where assertion of the iro1 or iro2 signal causes the software to perform i/o read access to address 60h, the hc intercepts this access and outputs the hceoutput value to the data bus instead of the keyboard controller. next, 0 is set to the outputfull field, and iro1 or iro2 is deasserted. by performing this series of operations, the software is able to handle usb keyboard/mouse data in the same way as legacy keyboard/mouse data.
chapter 3 description of usb host controller functions 47 figure 3-19 shows a flowchart for when input devices include a combination of usb keyboard or mouse devices and legacy keyboard or mouse devices. in this case, processing of the usb keyboard/mouse data uses the same flow as was described above. meanwhile, legacy keyboard/mouse data is passed to the system software in the same way as during emulation processing of usb keyboard/mouse data. when 1 has been set to externalirqen, if an interrupt signal from the keyboard controller is detected, 1 is set to either the irq1active bit or the irq12active bit in hcecontrol in response to the interrupt signal. when 1 is set to either of these bits, the hc no longer acknowledges i/o access. next, the hc checks that the memory access bit setting is 1, the irq1active or irq12active bit setting is 1, and the externalirqen bit setting is also 1, then generates an emulation interrupt. at the point when the system software detects the emulation interrupt, data is read from the keyboard controller via 60h i/o access and is written to hceoutput reg. (108h) via a memory write operation, then 1 is set to the outputfull field. at the point when the system software confirms assertion of iro1 (irq1) or iro2 (irq12), the hc clears irq1active or irq12active to 0 so that it is again able to respond to i/o access. after this change, assertion of the iro1 or iro2 signal enables i/o read access to 60h. when i/o read access to 60h in software is performed, the hc intercepts this access and outputs the hceoutput value to the data bus instead of the keyboard controller, and it sets 0 to outputfull and deasserts iro1 or iro2. during emulation, interrupts from the keyboard controller are masked and are not received. figure 3-19. combination of usb keyboard/mouse and legacy keyboard/mouse (input emulation) iri1 = irq1active ? 1 iri2 = irq12active ? 1 ir note 4 = 1:smi ? 0 ir note 4 = 0:inta ? 0 aof note 6 = 0:ir01 ? 1 aof note 6 = 0:ir02 ? 1 i/o access to hc disable emulation for usb keyboard/mouse i/o 60h read irqen = 1& outputfull = 1 finished emulation done finished keyboard/mouse data from legacy products. emulation enable = 1& operated usb keyboard/mouse i rq1active ? 0 irq12active ? 0 emulationenable ? 1 smi or inta ? 1 i/o access to hc enable yes no yes no yes no hceoutput ? data from keyboard output full ? 1 keyboard date:auxoutputfull ? 0 mouse date:auxoutputfull ? 1 s oftware (hdc, bios, driver) proceed ma note 1 = 1?& (irq1a note 2 = 1?or irq12a note 3 = 1?) i/o 60h ? accessintercept ad ? hceoutput outputfull ? 0 ir01 ? 0, ir02 ? 0 notes 1. ma = pci command reg. memory access 2. irq1a = irq1active 3. irq12a = irq12active 4. ir = interruptrouting 5. an emulation interrupt is set independently of emulationenable. 6. aof = auxoutputfull
chapter 3 description of usb host controller functions 48 figure 3-20 shows a legacy operation flowchart for output operations. when emulationenable is 0, only legacy keyboard or mouse devices are valid. consequently, the hc does not receive i/o access and write operations to i/o address 60h/64h are performed directly from the keyboard controller. when emulationenable is 1, the hc intercepts the write operation to i/o address 60h/64h and writes the data to hceinput, then sets 1 to hcestatuss inputfull field. in addition, it sets 0 to hcestatuss cmddata field when data is written to 60h, and it sets 1 to that field when data is written to 64h. once the hc confirms that 1 has been set to memoryaccess, inputfull, and emulationenable, it generates an emulation interrupt. when writing to a usb keyboard or mouse, the system software reads from hceinput upon detecting the emulation interrupt, and then sets 0 to inputfull. next, the system software generates data in the td and usb formats, based on the data that was read, and processes this data via ordinary usb operations. meanwhile, when writing to a legacy keyboard or mouse, the system software not only reads hceinput and sets 0 to inputfull, it also sets 0 to emulationenable. since setting 0 to emulationenable means that the hc no longer receives i/o access, writing to i/o address 60h or 64h is performed by writing directly to the keyboard controller. the value of cmddata is checked to determine whether output is to i/o address 60h or 64h. if a gatea20 sequence occurs, it takes priority over the operations described above. figure 3-20. output-related legacy operation flowchart ir note 2 = 1:smi ? 0 ir note 2 = 0:inta ? 0 i/o access to hc disable i/o access to hc enable hceinput ? ad inputfull ? 1 emulation for usb keyboard/mouse emulation for legacy keyboard/mouse legacy support output write to i/o 60h/64h write to i/o 60h/64h gatea20 sequence ma note 1 = 1?& inputfull = 1? emulationenable = 1? data to keyboard controller finished gatea20 sequence write to i/o 60h: cmddata ? 0 write to i/o 64h: cmddata ? 1 yes no yes yes no no s oftware (hdc, bios, driver) proceed notes 1. ma = pci command reg. memory access 2. ir = interruptrouting
chapter 3 description of usb host controller functions 49 figure 3-21. distinctions between legacy and usb ir note = 1:smi ? 1 ir note = 0:inta ? 1 i/o access to hc disable ir note = 1:sm ? 1 ir note = 0:inta ? 1 emulation for usb keyboard/mouse emulation for legacy keyboard/mouse emulation done data to keyboard controller read hceinput emulationenable ? 0 read hceinput make usb td inputfull ? 0 cmddata = 0: i/o write hceinput data to 60h cmddata = 1: s oftware (hdc, bios, driver) proceed note ir = interruptrouting gatea20 sequences occur frequently in dos applications, where they mainly set a20 as valid or invalid. to reduce the number of smis that occur due to gatea20, the hc generates an smi (system management interrupt) only when the gatea20 status is to be changed by a gatea20 sequence. table 3-5 lists operation conditions and hc operations. table 3-5. gatea20 sequences condition hc gatea20 sequence value written to i/o (64h) value written to i/o (64h) (bit 1) gatea20 sequence inputfull 10 d1h 0 ? 1 0 2 0 ffh 0 1 3 0 except d1h/ffh 0 1 41 d1h 1 0 5 1 ffh 1 ? 00 6 1 except d1h/ffh 1 ? 01 7 1 value does not match a20state 1 1 8 1 value matches a20state 1 0 the system software first sets the a20state for hcecontrol. next, it sets the gatea20 sequence as valid by writing d1h to i/o (64h), which sets gatea20sequence for hcecontrol. when gatea20sequence has been set, any data whose bit 1 value is not a20state is written to i/o port 60h and inputfull is set. at that point, hc confirms that ?1? has been set to memoryaccess, inputfull, and emulationenable, after which an interrupt occurs. when the system software detects this interrupt, processing of gatea20 begins.
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51 chapter 4 power management 4.1 overview of power management this device supports clkrun functions and pci/usb clock stop functions in order to reduce power consumption. this chapter describes the power management approach and related control methods.
chapter 4 power management 52 4.2 bus states and device states in this device, power management provides separate control of pci and usb operations. therefore, to understand these operations, one must first understand the pci bus states, usb bus states, and device states. (1) pci bus states b0: pci clk = 33 mhz (includes clkrun operations) b1: pci clk = intermittent clock operation mode b2: pci clk = stop, pci bus power on b3: pci clk = stop, pci bus power off (2) usb bus states usb_reset: bus = reset, usb system is stopped (except for state transition monitoring) this state is entered when reset mode is canceled. this state can also be entered based on usb operational register settings. usb_operational: bus = active, usb system is operating normally this state can be entered based on usb operational register settings. usb_suspend: bus = suspend, usb system is stopped (except for bus state and state transition monitoring) this state can be entered based on usb operational register settings. the state transition can also be caused by s/w_reset. usb_resume: bus = resume, usb system is operating normally this state can be entered based on usb operational register settings. the state transition can also be caused by connecting or disconnecting devices or by a wakeup request from a connected device. (3) device states d0 : normal operation mode (pci = b0, usb = reset, operational, suspend, or resume) the pci state must be b0, usb state can be any state. d2 : device sleep mode (pci = b0, b1, or b2; usb = reset, suspend/resume) the pci state can be normal operation, intermittent operation, or suspended operation, but the cpu can access the hc's configuration space and operational registers only during the normal operation state. this restriction exists in order to maintain synchronous periods between the hc and the hcd. the system software and hcd should be coordinated to provide contrast so as to prevent hc operation faults. while in this mode, if the usb state is suspend, a wakeup operation occurs if a new device connection or disconnection is detected or if the resume state is entered in response to a resume signal. d3 : device disable mode (pci clock stop, usb = reset, or power off) the pci state can be normal operation, intermittent operation, or suspended operation, but the cpu can access the hc's configuration space and operational registers only during the normal operation state. this restriction exists in order to maintain synchronous periods between the hc and the hcd. the system software and hcd should be coordinated to provide contrast so as to prevent hc operation faults. wakeup operations do not occur.
chapter 4 power management 53 4.3 transition conditions for bus states and device states the following conditions must be met for a device state transition to occur. table 4-1. device state transition conditions state transition transition condition transition request source d0 ? d2 register setting specifies usb = usb_reset or suspend state system d0 ? d3 register setting specifies usb = usb_reset state and device's power is off or a hw_reset occurs system d2 ? d0 register setting system, usb_wakeup d3 ? d0 register setting system d2 ? d3 register setting specifies usb = usb_reset state and device's power is off or a hw_reset occurs system usb state transitions are defined in the usb specifications. the transition conditions are listed below. table 4-2. usb state transition conditions transition condition state transition operational register setting h/w_reset s/w_reset wakeup request attach detection dettach detection operational ? reset {{ suspend ? reset {{ resume ? reset {{ reset ? operational { operational ? suspend { { suspend ? operational { suspend ? resume { {{{ resume ? operational { reset ? suspend { resume ? suspend { remark wakeup: wakeup request from usb device the mutual relation between the device and the external (usb or pci) interface is determined as follows, according to the previously described relations between the pci bus and the device state as well as the device/usb state transition information.
chapter 4 power management 54 table 4-3. mutual relation between device state and pci or usb device state pci state usb state source of request from usb to pci control output operational transaction reset suspend - d0 b0 resume wakeup/attach/dettach inta smi req crun reset suspend -- b0 resume wakeup/attach/dettach wake reset suspend -- b1 resume wakeup/attach/dettach wake reset suspend -- d2 b2 resume wakeup/attach/dettach wake b0 reset -- b1 reset -- b2 reset -- d3 b3 reset -- remarks 1. the inta signal operates completely asynchronously in relation to the pci clock. 2. when the device state is d2, the usb state must be a state other than operational. 3. when the device state is d3, the usb state must be reset, the hc must be in power-off state, or an hw_rst must occur.
chapter 4 power management 55 4.4 device state transition flow to prevent faults in usb control operations from occurring due a transition between device states, such control operations must follow a predetermined flow during a state transition. make sure that such transitions comply with the device state transition flow described in table 4-4 below. also, make sure that the hcd and system processing comply with the openhci specifications. table 4-4. state control device state usb state state transition control suspend ? resume transition is only when resume signal is sent from usb flow a operational (bus master req) flow b operational (interrupt event) flow a operational (write to internal register) flow c d0 (pci = clkrun) all other transitions normal hcd control d2 suspend ? resume flow d d3 no transition none d0 ? d2 all transitions flow e d0 ? d3 all transitions flow f d2 ? d3 reset, suspend flow f d2 ? d0 reset, suspend request from system flow g usb wakeup request flow d d3 ? d0 reset don?t care flow a (a) assert inta (hc) (b) normal clock supply (system) (c) interrupt servicing (system) (d) deassert inta (hc) inta output is synchronized to a 12-mhz clock and there is a delay of up to 170 ns between clearing of the status register and clearing of inta. flow b (a) assert crun (only when clkrun# is at high level) (hc) (b) normal clock supply (system) (c) assert req (hc) (d) pci bus master operation (hc) (e) deassert req (hc) (f) multiple clock continues operation using crun, when necessary (hc) the maximum allowable time between assertion of crun and assertion of gnt to a device is 7 m s. this is a restriction that applies to req for cases where data that includes at least 64 bytes is transferred via an isochronous transaction. if more than 7 m s elapses before processing is started, some isochronous data may be lost during transfer. see the specifications of pci mobile design guide for crun operations.
chapter 4 power management 56 flow c (a) assert crun (only when clkrun# is at high level) (hc) (b) normal clock supply (system) (c) multiple clock continues operation using crun, when necessary (hc) the maximum allowable time between assertion of crun and reset to normal clock operation is 5 m s. see the specifications of pci mobile design guide for crun operations. flow d (a) send resume signal from usb (only when hcfs = usb_suspend) (usb) (b) assert wake and set wakeupstatus (hc) (c) reset to wakeup processing and normal clock (system) (d) clear wakeupstatus (system) (e) deassert wake (hc) (f) set device state to d0 and wakeup enable to 0 (system) (g) assert inta (hc) (h) interrupt servicing (system) (i) deassert inta (hc) inta and wake output are synchronized to a 12-mhz clock and there is a delay of up to 170 ns between clearing of the status register and clearing of inta or wake. flow e (a) set hcfs in hccontrol register to usb_reset or usb_suspend (hcd) (b) set device state to d2 (system) (c) set statuschangestandby bit (hc) (d) set wakeup enable to 1 (system) (e) enable pci bus state change (system) when the pci bus state changes, the system must wait until the statuschangestandby bit in the power management control/status register goes high. when activating a wakeup via a resume signal from the usb, the hcfs must be set to usb_suspend. flow f (a) set hcfs in hccontrol register to usb_reset (hcd) (b) set device state to d3 (system) (c) set statuschangestandby bit (hc) (d) enable pci bus state change (system) when the pci bus state changes, the system must wait until the statuschangestandby bit in the power management control/status register goes high. other methods for setting a transition to the d3 state include using power-off or hw_rst. if using hw_rst, make sure that synchronization is maintained between the hcd and the hc. in the case of a transition to d3 using hw_rst, the device does not acknowledge any kind of pci access. after hw_rst is cleared, the device state is d0.
chapter 4 power management 57 flow g (a) normal clock supply (system) (b) set device state to d0 and wakeup enable to 0 (system) special device controls are not required when resetting from the d3 device state via system power-off or an hw_rst.
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59 chapter 5 register information 5.1 pci configuration space the configuration register is accessed in order to set up hardware resources, device characteristics or operations, etc. in pci local bus. this chapter describes the pci configuration space, which is the address space for the configuration register. for a more detailed description, see the pci local bus specification revision 2.1 . table 5-1. pci configuration space 31 24 23 16 15 8 7 0 offset device id vender id 00h status command 04h class code revision id 08h bist header type latency timer cache line size 0ch bar_ohci register 10h i/o address register (pc/at tm ) 14h i/o address register (pc-98 series) 18h 1ch 20h base address register 24h cardbus cis pointer 28h subsystem id subsystem v ender id 2ch expansion rom base address 30h reserved 34h reserved 38h max_lat min_gnt interrupt pin interrupt line 3ch 40h . . reserved dfh power management control/status e0h
chapter 5 register information 60 table 5-2. register information register address bits read/ write value (default) comment vender id 00h 15 : 0 r 1033h necs vendor id device id 02h 15 : 0 r 0035h this devices device id command 04h 15 : 0 see table 5-1. status 06h 15 : 0 see table 5-4. revision id 08h 7 : 0 r 02h version 2.0 23 : 16 r 0ch serial bus controller device 16 : 8 r 03h usb device 7 : 0 r 10h open hci host controller class code-base class -sub_class -programming interface 09h cache line size 0ch 7 : 0 r 00h cache disabled 7 : 3 r/w 00000b latency timer 0dh 2 : 0 r 000b time to continuation of bus cycle header type 0eh 7 : 0 r 00h not a pci-to-pci bridge bist 0fh 7 : 0 r 00h bist is not supported. base address register 10h 31 : 0 see table 5-5. i/o address register (pc/at) 14h 31 : 0 see table 5-6. i/o address register (pc-98 series) 18h 31 : 0 n.a. subsystem v ender id 2ch 15 : 0 r (/w) 0000h subsystem id 2eh 15 : 0 r (/w) 0000h write enabled, according to setting of id write mask bit interrupt line 3ch 7 : 0 r/w 00h indicates interrupt lines route interrupt pin 3dh 7 : 0 r 01h application of inta# min_gnt 3eh 7 : 0 r 01h minimum request time for burst cycle max_lat 3fh 7 : 0 r 15h frequency of bus access requests table 5-3. command register information field bit read/ write value (default) comment i/o space 0 r/w 0b controls responses to i/o access memory space 1 r/w 0b controls responses to memory access bus master 2 r/w 0b controls bus master operations special cycles 3 r 0b ignores special cycles memory write and invalidate enable 4 r 0b sets memory write and invalidate as invalid vga palette snoop 5 r 0b sets vga palette snoop as invalid parity error response 6 r/w 0b controls response to parity error wait cycle control 7 r 0b address/data st epping is not supported. serr# enable 8 r/w 0b controls responses to system errors fast back-to-back enable 9 r 0b fast back-to-back access is not supported. reserved 15 : 10 r 000000b reserved
chapter 5 register information 61 table 5-4. status register information field bit read/ write value comment reserved 4 : 0 r 00000b reserved 66mhz capable 5 r 0b 33-mhz operation udf supported 6 r 0b udf is not supported. fast back-to-back capable 7 r 0b fast back-to-back access is not supported. data parity error detected 8 r/w 1 is set to this bit when the following three conditions are met. (1) either perr# was asserted by the parity error source or assertion of perr# by the target source was detected. (2) the parity error source was the bus master during the bus cycle in which the data parity error occurred. (3) 1 has been set to the command registers parity error response bit. devsel timing 10 : 9 r 01b devsel# assert timing: medium speed signaled target abort 11 r/w the target sets 1 if the bus cycle it is accessing ends due to a target abort condition. received target abort 12 r/w the master sets 1 if the bus cycle it is executing ends due to a target abort condition. received master abort 13 r/w the master sets 1 if the bus cycle it is executing ends due to a master abort condition. signaled system error 14 r/w 1 is set to this bit w hen serr# is asserted. detected parity error 15 r/w 1 is set to this bit when data parity or address parity is detected. table 5-5. base address (bar_ohci) register information field bit read/ write value (default) comment memory space indicator 0 r 0b operational registers are mapped to main memory space. type 2 : 1 r 00b operational registers can be allocated in any part of the 4-g main memory space. prefetchable 3 r 0b prefetch is disabled. base address (lsb) 11 : 4 r 00h operational registers have a 4-kbyte address space. base address (msb) 31 : 12 r/w 000h indicates the high-order 20 bits of the base address in the operational registers.
chapter 5 register information 62 table 5-6. i/o address register (pc/at) information field bit read/ write value (default) comment i/o space indicator 0 r 1b legacy register is mapped to the i/o space. reserved 1 r 0b reserved base address (lsb) 2 r 0b legacy register has an 8-byte address space. base address (msb) 31 : 3 r/w 000h indicates the high-order 29 bits of the base address in the legacy register. remark the i/o address register is fixed to 0h when legacy support is invalid. on the other hand, when legacy support is valid, the i/o address register (pc-98 series: offset address 18h) is fixed at 0h. table 5-7. power management control/status information field bit read/ write value (default) comment power state 1 : 0 r/w 00b power state control bit 00b = d0 (pci clk full mode: default) 01b = reserved 10b = d2 (pci clk stop and device power on) 11b = d3 (pci clk stop and device power off) status change standby 2 r 0b indicates the device state in relation to control of power state transitions 0b = not ready 1b = ready bus master control 3 r/w 0b controls pci command registers bit 2 (bus master bit) 0b = bus master bit is invalid (ordinary bus master operation) 1b = bus master bit is valid reserved 4 r 0b reserved req_enable 5 r/w 0b req signal output timing control 0b = pci clock synchronous output: default 1b = pci clock asynchronous output pc_mode 6 r/w 0b pc-98 series / pc/at switch setting control 0b = pc-98 series mode: default 1b = pc/at mode id write mask 7 r/w 0b write protection of subsystem id and sub system vendor id 0b = write mask: default 1b = write enable wakeup_status 8 r/w 0b 1 is set when a wakeup request has been issued. writing 1 clears the bit, but writing 0 does not change it. reserved 15 : 9 r 0b reserved wakeup_enable 16 r/w 0b output control of wake signal 0b = wake signal is invalid: default 1b = wake signal is valid reserved 31 : 17 r 0b reserved
chapter 5 register information 63 remarks 1. be sure to use req_enable the default. if used asynchronously, it may no longer comply with the pci specifications. 2. the power state bit is invalid when pc_mode = 0. the system has read/write access to the power state bit. the hc has read-only access. 3. the wakeup_status bit is invalid when pc_mode = 0. when pc_mode = 1, power state = 10, and hcfs = u sb s uspend , 1 is set when a resume signal from the usb is detected. at that point, if the wakeup_enable bit = 1, the wake signal is asserted. writing 1 clears this bit and simultaneously deasserts wake. the above operations occur only when the hcinterruptenable registers rhsc/rd bit has been set. 4. the wakeup_enable bit is invalid when pc_mode = 0. 5. after the power state bit has been set as d2 or d3, 0 is output as the status change standby value until the state transition is actually ready to occur, after which 1 is output. once the status change standby value becomes 1 after the power state bit has been set as d2 or d3, it does not revert back to 0. this bits value is always 0 when the power state bit has been set as d0. 6. the bus master control bit switches the command registers bus master bits valid/invalid setting. when the bus master control bits value is 0, bus master operations are valid whether or not the bus master bits value is set to 0. figure 5-1. openhcis pci configuration space ? command pci device ? class_code ? bar_ohci ? mode operational registers openhci hcca status event frame int ratio control bulk interrupt 0 host controller communications area device register in memory space shared ram interrupt 1 ? interrupt 2 interrupt 31 ? done the pci configuration space?s base address (bar_ohci) register is in an openhci-compliant host controller. it indicates the base address of operational registers which are the starting point for communication with the host cpu.
chapter 5 register information 64 5.2 operational registers the host controller includes the operational registers, which are the starting point for communication with the host cpu. this set of registers is mapped to a 4-kbyte range in the 4-gbyte main memory space, where it is used by the hcd (host controller driver). all of the registers in this set are read from or written to in dword units. for a more detailed description, see the open hci specification release 1.0 and openhci legacy support interface specification release version 1.01 . table 5-8. host controller operational registers 31 0 offset hcrevision 00h hccontrol 04h hccommandstatus 08h hcinterruptstatus 0ch hcinterruptenable 10h hcinterruptdisable 14h hchcca 18h hcperiodcurrented 1ch hccontrolheaded 20h hccontrolcurrented 24h hcbulkheaded 28h hcbulkcurrented 2ch hcdonehead 30h hcfminterval 34h hcfmremaining 38h hcfmnumber 3ch hcperiodicstart 40h hclsthreshold 44h hcrhdescriptora 48h hcrhdescriptorb 4ch hcrhstatus 50h hcrhportstatus1 54h hcrhportstatus2 58h table 5-9. legacy support registers 31 0 memory offset i/o address hcecontrol 100h hceinput 104h 60h/64h hceoutput 108h 60h hcestatus 10ch 64h
chapter 5 register information 65 5.2.1 overview of operational registers register: hcrevision offset address: 00h read/write field bit hcd hd value (default) comment revision 7 : 0 r r 10h complies with openhci r1.0 legacy 8 r r/w xb includes a legacy support register. it is set to suit the setting of external pin legc. legc = 0 ? set to ?0? legc = 1 ? set to ?1? reserved 31 : 9 r/w r xh reserved register: hccontrol offset address: 04h read/write field bit hcd hd value (default) comment indicates the control/bulk service ratio between eds. cbsr no. of control eds over bulk eds served 0 1 : 1 1 2 : 1 2 3 : 1 3 4 : 1 controlbulkserviceratio (cbsr) 1 : 0 r/w r 00b periodiclistenable (ple) 2 r/w r 0b sets the next frames periodic list servicing as valid or invalid. 1: valid, 0: invalid isochronousenable (ie) 3 r/w r 0b sets the next frames isochronous ed servicing as valid or invalid. 1: valid, 0: invalid controllistenable (cle) 4 r/w r 0b sets the next frames control list servicing as valid or invalid. 1: valid, 0: invalid bulklistenable (ble) 5 r/w r 0b sets the next frames bulk list servicing as valid or invalid. 1: valid, 0: invalid hostcontrollerfunctionalstate for usb (hcfs) 7 : 6 r/w r/w 00b (h/w_r note 1 ) 11b (s/w_r note 2 ) 00b: u sb r eset 01b: u sb r esum 10b: u sb o perational 11b: u sb s uspend interruptrouting (ir) note 3 8 r/w r 0b this bit indicates the route of an interrupt that is triggered by an event registered in hclnterruptstatus. 1: smi output, 0: int output remotewakeupconnected (rwc) note 3 9 r/w r/w 0b this bit indicates whether or not remote wakeup signals are supported. 1: supported, 0: not supported remotewakeupenable (rwe) 10 r/w r 0b sets remote wakeup signal as valid or invalid when upstream resume signal is detected. reserved 31 : 11 r/w r xh reserved notes 1. h/w_r = hardware reset 2. s/w_r = software reset 3. only hardware reset is available.
chapter 5 register information 66 register: hccommandstatus offset address: 08h read/write field bit hcd hd value (default) comment hostcontrollerreset (hcr) 0 r/w r/w 0b hc software reset. this bit is set by the hcd and cleared by the hc. controllistfilled (clf) 1 r/w r/w 0b indicates whether or not a td exists in the control list. bulklistfilled (blf) 2 r/w r/w 0b indicates whether or not a td exists in the bulk list. ownershipchangerequest (ocr) 3 r/w r/w 0b this bit is set by the hcd to request modification of hc control. reserved 15 : 4 r/w r xh reserved schedulingoverruncount (soc) 17 : 16 r r/w 00b this bit is incremented when a scheduling overrun error occurs. it is initialized by 00b and is returned to its previous value by 11b. reserved 31 : 18 r/w r xh reserved register: hcinterruptstatus offset address: 0ch read/write field bit hcd hd value (default) comment schedulingoverrun (so) 0 r/w r/w 0b this bit is set when an overrun occurs during usb scheduling of the current frame. writebackdonehead (wdh) 1 r/w r/w 0b this bit is set when hcdonehead has been written to hccadonehead. the hcd clears this bit after the contents of hccadonehead have been saved. startofframe (sf) 2 r/w r/w 0b this bit is set at the start of a frame. resumedetected (rd) 3 r/w r/w 0b this bit is set when a resume signal has been detected. unrecoverableerror (ue) 4 r/w r/w 0b this bit is set when a system error that is unrelated to usb has been detected. framenumberoverflow (fno) 5 r/w r/w 0b this bit is set when the value of the msb (bit 15) of hcfmnumber has changed from 0 to 1 or from 1 to 0. roothubstatuschange (rhsc) 6 r/w r/w 0b this bit is set when the contents of either hcrhstatus or hcrhportstatusx are changed. reserved 29 : 7 r/w r xh reserved ownershipchange (oc) 30 r/w r/w 0b this bit is set by the hc when the hcd has set the ocr field in the hccommandstatus register. if this event is not masked, it immediately triggers a system m anagement interrupt (smi). other 31 r r 0b
chapter 5 register information 67 register: hcinterruptenable offset address: 10h read/write field bit hcd hd value (default) comment so 0 r/w r 0b 0: ignore 1: interrupt is triggered by scheduling overrun wdh 1 r/w r 0b 0: ignore 1: interrupt is triggered by hcdonehead writeback sf 2 r/w r 0b 0: ignore 1: interrupt is triggered by start of frame rd 3 r/w r 0b 0: ignore 1: interrupt is triggered by resume detect ue 4 r/w r 0b 0: ignore 1: interrupt is triggered by unrecoverable error fno 5 r/w r 0b 0: ignore 1: interrupt is triggered by frame number overflow rhsc 6 r/w r 0b 0: ignore 1: interrupt is triggered by root hub status change reserved 29 : 7 r/w r xh reserved oc 30 r/w r 0b 0: ignore 1: interrupt is triggered by ownership change master interrupt enable (mie) 31 r/w r 0b 0: ignore 1: interrupt triggering is enabled when an event other than those listed above occurs. register: hcinterruptdisable offset address: 14h read/write field bit hcd hd value (default) comment so 0 r/w r 0b 0: ignore 1: interrupt is not triggered by scheduling overrun wdh 1 r/w r 0b 0: ignore 1: interrupt is not triggered by hcdonehead writeback sf 2 r/w r 0b 0: ignore 1: interrupt is not triggered by start of frame rd 3 r/w r 0b 0: ignore 1: interrupt is not triggered by resume detect ue 4 r/w r 0b 0: ignore 1: interrupt is not triggered by unrecoverable error fno 5 r/w r 0b 0: ignore 1: interrupt is not triggered by frame number overflow rhsc 6 r/w r 0b 0: ignore 1: interrupt is not triggered by root hub status change reserved 29 : 7 r/w r xh reserved oc 30 r/w r 0b 0: ignore 1: interrupt is not triggered by ownership change master interrupt enable (mie) 31 r/w r 0b 0: ignore 1: interrupt triggering is disabled when an event other than those listed above occurs.
chapter 5 register information 68 register: hchcca offset address: 18h read/write field bit hcd hd value (default) comment 7 : 0 r r 00h host controller communication area (hcca) 31 : 8 r/w r 0h this is the base address of the host controller communication area. since it is allocated in 256-byte units, the low-order 8 bits are fixed at 0. register: hcperiodcurrented offset address: 1ch read/write field bit hcd hd value (default) comment 3 : 0 r r 00h periodcurrented (pced) 31 : 4 r r/w 0h this is the physical address of an isochronous or interrupt ed in the periodic list being serviced during the current frame. since the ed is allocated in 16-byte units, the low-order 4 bits are fixed at 0. register: hccontrolheaded offset address: 20h read/write field bit hcd hd value (default) comment 3 : 0 r r 00h controlheaded (ched) 31 : 4 r/w r 0h this is the physical address of the first ed in the control list. register: hccontrolcurrented offset address: 24h read/write field bit hcd hd value (default) comment 3 : 0 r r 00h controlcurrented (cced) 31 : 4 r/w r/w 0h this is the physical address of the current ed in the control list. register: hcbulkheaded offset address: 28h read/write field bit hcd hd value (default) comment 3 : 0 r r 00h bulkheaded (bhed) 31 : 4 r/w r 0h this is the physical address of the first ed in the bulk list. register: hcbulkcurrented offset address: 2ch read/write field bit hcd hd value (default) comment 3 : 0 r r 00h bulkcurrented (bced) 31 : 4 r/w r/w 0h this is the physical address of the current ed in the bulk list.
chapter 5 register information 69 register: hcdonehead offset address: 30h read/write field bit hcd hd value (default) comment 3 : 0 r r 00h donehead (dh) 31 : 4 r r/w 0h this is the physical address of the last td to be added to the done queue. register: hcfminterval offset address: 34h read/write field bit hcd hd value (default) comment frameinterval (fi) 13 : 0 r/w r 2edfh this bit indicates a bit time value for the time interval per frame. reserved 15 : 14 r/w r xh reserved fslargestdatapacket (fsmps) 30 : 16 r/w r 0000h this is the maximum number of data bits that can be sent or received in one transaction. frameintervaltoggle (fit) 31 r/w r 0b this is inverted when loading to fi. register: hcfmremaining offset address: 38h read/write field bit hcd hd value (default) comment frameremaining (fr) 13 : 0 r r/w 0h this is a 14-bit down counter which indicates the remaining bit time in the current frame. reserved 30 : 14 r/w r xh reserved frameremainingtoggle (frt) 31 r r/w 0b when the value of fr becomes 0, a value is loaded from the fit field of the hcfminterval register. register: hcfmnumber offset address: 3ch read/write field bit hcd hd value (default) comment framenumber (fn) 15 : 0 r r/w 0h this is a 16-bit counter that is incremented when hcfmremaining is reloaded. reserved 31 : 16 r/w r xh reserved register: hcperiodicstart offset address: 40h read/write field bit hcd hd value (default) comment periodicstart (ps) 13 : 0 r/w r 0h this indicates that periodic list servicing should be started. the standard value is 3e67h. reserved 31 : 14 r/w r xh reserved
chapter 5 register information 70 register: hclsthreshold offset address: 44h read/write field bit hcd hd value (default) comment lsthreshold (lst) 11 : 0 r/w r 0628h this includes a value that is used to determine whether or not to send the ls packet before the eof token. reserved 31 : 12 r/w r xh reserved register: hcrhdescriptora offset address: 48h read/write field bit hcd hd value (default) comment numberdownstreamports (ndp) note 7 : 0 r r 02h this bit indicates the number of downstream ports that are supported by the root hub. powerswitchingmode (psm) note 8 r/w r 1b 0: power supply is applied to all ports at the same time. 1: power supply is applied separately to each port. nopowerswitching (nps) note 9 r/w r 0b 0: power supply to ports can be switched on and off. 1: power supply to ports is always applied when hcs power is on. devicetype (dt) note 10 r r 0b indicates that the root hub is not a hybrid type of device. overcurrentprotectionmode (ocpm) note 11 r/w r 1b 0: overcurrent status is reported to all downstream ports at once. 1: overcurrent status is reported separately to each port. noovercurrentprotection (nocp) note 12 r/w r 0b 0: overcurrent status is reported. 1: overcurrent protection is not supported. reserved 23 : 13 r/w r xh reserved powerontopowergoodtime (potpgt) note 31 : 24 r/w r ffh this bit indicates the amount of time that the hcd must wait before accessing the root hub port to which a power supply is applied. note this field can only be used for hardware resets. register: hcrhdescriptorb offset address: 4ch read/write field bit hcd hd value (default) comment deviceremovable (dr) note 15 : 0 r/w r 0000h bit0: reserved bit1: device is connected to port#1 bit2: device is connected to port#2 bit15: device is connected to port#15 portpowercontrolmask (ppcm) note 31 : 16 r/w r fffeh bit0: reserved bit1: power supply to port#1 set is masked bit2: power supply to port#2 set is masked bit15: power supply to port#15 set is masked note this field can only be used for hardware resets. ? ?
chapter 5 register information 71 register: hcrhstatus offset address: 50h read/write field bit hcd hd value (default) comment localpowerstatus (lps) note r r 0b the root hub does not support local power status. clearglobalpower (cgp) note 0 w r 0b 1: power supply to all ports is off when psm = 0. when psm = 1, only pps is cleared for ports where ppcm has not been set. 0: no change overcurrentindicator (oci) note 1 r r/w 0b the following occurs when overcurrent status is reported to all downstream ports at once. 1: overcurrent status exists 0: normal power supply operations be sure that this is set to 0 when overcurrent status is to be reported to each port. reserved 14 : 2 r/w r xh reserved deviceremotewakeupenable (drwe) note r r 0b 0: csc is not a remote wakeup event 1: csc is a remote wakeup event setremotewakeupenable (srwe) note 15 w r 0b 1: sets rwe 0: no change localpowerstatuschange (lpsc) note r r 0b the root hub does not support local power status. setglobalpower (sgp) note 16 w r 0b 1: power supply to all ports is on when psm = 0. when psm = 1, only pps is set for ports where ppcm has not been set. 0: no change overcurrentindicatorchange (ccic) note 17 r/w r/w 0b hc sets 1 when a change has occurred in oci. it is cleared when the hcd writes 1. there is no change when the hcd writes 0. reserved 30 : 18 r/w r xh reserved clearremotewakeupenable (crwe) note w r 0b 1: clears rwe 0: no change other 31 rr 0b note this field can only be used for hardware resets.
chapter 5 register information 72 register: hcrhportstatus [1:2] offset address: 54h, 58h read/write field bit hcd hd value (default) comment currentconnectstatus (ccs) note 0 r r/w 0b this bit is set when a device has been connected. this bit is cleared when the device is disconnected or when the power to the port is turned off. portenablestatus (pes) note 1 r r/w 0b this bit is set by the following conditions. ? when spe is issued while ccs = 1 ? when prsc is set ? when pssc is set it is cleared by the following conditions. ? when an overcurrent occurs ? when a device is disconnected ? when the ports power is off ? when an operational error, such as bubble detection, occurs ? when cpe is issued portsuspendstatus (pss) note 2 r r/w 0b this bit is set when sps is issued while ccs = 1. it is cleared when pssc or prsc is set, when hcfs = 01b, or when the ports power is off. portovercurrentindicator (poci) note 3 r r/w 0b this bit is set when an overcurrent has occurred while nocp = 0 and ocpm = 1. it is cleared when the setting condition is canceled. portresetstatus (prs) note 4 r r/w 0b this bit is set when spr is issued while ccs = 1. it is cleared when pssc or prsc is set, when hcfs = 01b, or when the ports power is off. portpowerstatus (pps) note 8 r r/w 0b this bit is set by the following conditions. ? when sgp is issued while nps = 1 or nps = 0, and psm = 0. ? when sgp is issued while nps = 0, psm = 1, and the corresponding bit in ppcm = 0 ? when spp is issued while nps = 0, psm = 1, and the corresponding bit in ppcm = 1 it is cleared by the following conditions. ? when cgp is issued while nps = 1 or nps = 0, and psm = 0 ? when cgp is issued while nps = 0, psm = 1, and the corresponding bit in ppcm = 0 ? when cpp is issued while nps = 0, psm = 1, and the corresponding bit in ppcm = 1 ? when an overcurrent occurs lowspeeddeviceattached (lsda) note 9 r r/w 0b this bit is set when a low-speed device is connected. it is cleared when a full-speed device is connected. connectstatuschange (csc) note 16 r/w r/w 0b this bit is set by the following conditions. ? by a change in ccs or by setting of the corresponding bit in dr ? spr/spe/sps is issued when ccs = 0. it is cleared when 1 is written by the hcd.
chapter 5 register information 73 read/write field bit hcd hd value (default) comment portenablestatuschange (pesc) note 17 r/w r/w 0b this bit is set by the following conditions. ? when an overcurrent occurs ? when a device is disconnected ? when a ports power is off ? when an operational error, such as bubble detection, occurs it is cleared when 1 is written by the hcd. portsuspendstatuschange (pssc) note 18 r/w r/w 0b this bit is set by completion of a resume signal. it is cleared when 1 is written by the hcd or when prsc is set. portovercurrentindicator change (ocic) note 19 r/w r/w 0b this bit is set when poci changes. it is cleared when 1 is written by the hcd. portresetstatuschange (prsc) note 20 r/w r/w 0b this bit is set by completion of a reset signal. it is cleared when 1 is written by the hcd. note this field can only be used for hardware resets.
chapter 5 register information 74 5.2.2 overview of legacy support registers read/write register memory address offset i/o address hcd comment hcecontrol 100h r/w this register is used to transmit various types of status information such as setting emulation hardware as valid, and controlling it. 10ch r/w hcestatus 64h r this is the legacy status register for emulation. input from port 64h indicates the current value of hcestatus without causing other operations. 104h r/w 60h w hceinput 64h w this is the legacy input buffer register for emulation. output to port 60h sets 1 to inputfull and 0 to cmddata in the hcestatus register. output to port 64h sets 1 to inputfull and cmddata in the hcestatus register. 108h r/w hceoutput 60h r this is the legacy output buffer register for emulation in which software writes to a keyboard or mouse device. input from port 60h sets 0 to outputfull in the hcestatus register. remark when emulation is enabled (valid), the hcestatus, hceinput, and hceoutput registers can be accessed via i/o addresses 60h and 64h. register: hceinput read/write field bit hcd value (default) comment inputdata 7 : 0 r/w xh this bit retains the data that is written to i/o ports 60h and 64h when emulation is enabled. reserved 31 : 8 - xh reserved register: hceoutput read/write field bit hcd value (default) comment outputdata 7 : 0 r/w xh this bit retains the data that is returned when the application software reads from port 60h and emulation is enabled. reserved 31 : 8 - xh reserved
chapter 5 register information 75 register: hcestatus read/write field bit hcd value (default) comment outputfull 0 r/w 0b when i/o port 60h is read, 0 is set by the hc. when irqen has been set and auxoutputfull has been set to 0, irq1 occurs as long as this bits value is 1. when irqen has been set and auxoutputfull has been set to 1, irq12 occurs as long as this bits value is 1. when this bits value is 0 and hcecontrols characterpending value is 1, the emulation interrupt condition has been met. inputfull 1 r/w 0b 1 is set to this bit during an i/o write operation to address 60h and 64h, except in the case of the gatea20 sequence. when this bits value is 1, the emulation interrupt condition has been met as long as emulation is enabled. flag 2 r/w 0b this bit is used as a system flag which ordinary software uses to indicate warm/cold boot status. cmddata 3 r/w 0b 0 is set by the hc when writing to port 60h and 1 is set by the hc when writing to port 64h. inhibit switch 4 r/w 0b this bit indicates the status of the keyboard inhibit switch. it is set when the keyboard is disabled (inhibit status). auxoutputfull 5 r/w 0b 1 is set to outputfull when this bit is set to 1. irq12 is always asserted when the irqen bit has been set. timeout 6 r/w 0b this bit is used to indicate a timeout condition. parity 7 r/w 0b this bit indicates a keyboard/mouse data parity error. reserved 31 : 9 - xh reserved
chapter 5 register information 76 register: hcecontrol read/write field bit hcd value (default) comment emulationenable 0 r/w 0b when this bits value is 1, the host controller is able to perform legacy emulation. the host controller decodes access to i/o registers 60h and 64h and irq1 or irq12 occur if the access is acceptable. the host controller may also generate an emulation interrupt when necessary to call up the emulation software. emulationinterrupt 1 r - this bit is used to passively decode emulation interrupt conditions. this bit?s value becomes ?1? when emulation interrupt status is on. characterpending 2 r/w 0b when this bit has been set, an emulation interrupt occurs if the hcestatus register?s outputfull bit?s value is ?0?. irqen 3 r/w 0b when this bit has been set, the host controller generates irq1 or irq12 if the hcestatus register?s outputfull bit?s value is ?1?. specifically, irq1 occurs when the hcestatus register?s auxoutputfull bit?s value is ?0? and irq12 occurs when it is ?1?. externallrqen 4 r/w 0b when this bit?s value is ?1?, an emulation interrupt is triggered by irq1 and irq12 from the keyboard controller. the function that controls this bit does not depend on the setting of the emulationenable bit in this register. gatea20sequence 5 r/w 0b when d1h is written to i/o port 64h, this bit is set by the hc. when a value other than d1h is written to i/o port 64h, this bit is cleared. irq1active 6 r/w 0b this bit indicates when a positive transition has occurred for irq1 from the keyboard controller. software writes ?1? to this bit in order to clear this setting (to ?0?). nothing occurs when software writes ?0? to this bit. irq12active 7 r/w 0b this bit indicates when a positive transition has occurred for irq12 from the keyboard controller. software writes ?1? to this bit in order to clear this setting (to ?0?). nothing occurs when software writes ?0? to this bit. a20state 8 0b this bit indicates the current status of the keyboard controller?s gatea20. when gatea20sequence is active, this bit is used for comparison with the value that was written to 60h. reserved 31 : 9 -- this bit is reserved. it must always be set to ?0?.
77 chapter 6 electrical characteristics 6.1 buffer list 5 v schmitt buffer rst, sclk, at, legc 5 v i ol = 12 ma n-ch open drain buffer smi 5 v input buffer rcvbe 5 v excessive through current prevention buffer oci (2:1), iri1, iri2 5 v i ol = 6 ma output buffer ppon (2:1), wake 5 v i ol = 6 ma n-ch open drain buffer iro1, iro2, a20s 5 v pci interface (3-v pci interface with 5-v maximum voltage circuit) ad (31:00), cbe (3:0), par, frame, irdy, trdy, stop, idsel, devsel, req, gnt, perr, serr, inta, pclk, crun usb interface dp (2:1), dn (2:1) above, 5 v refers to a 3-v buffer that is 5-v tolerant (has 5-v maximum voltage). therefore, it is possible to have a 5-v connection for an external bus, but the output level will be only up to 3 v, which is the v dd voltage. similarly, 5 v pci above refers to a pci buffer that has a 5-v maximum voltage circuit which meets the 3-v pci standard; it does not refer to a pci buffer that meets the 5-v pci standard.
chapter 6 electrical characteristics 78 6.2 absolute maximum ratings table 6-1. absolute maximum ratings parameter symbol conditions rating unit power supply voltage v dd - 0.5 to +4.6 v input voltage, 5-v buffer v i 3.0 v v dd 3.6 v v i < v dd + 3.0 v - 0.5 to +6.6 v output voltage, 5-v buffer v o 3.0 v v dd 3.6 v v o < v dd + 3.0 v - 0.5 to +6.6 v usb common mode voltage v cm - 0.5 to +3.8 v operating ambient temperature t a 0 to +70 c storage temperature t stg - 65 to +150 c caution product quality may deteriorate if an absolute maximum rating is exceeded for even one parameter or even momentarily. absolute maximum ratings are the highest values at which physical damage will not occur. therefore, be sure that none of these maximum ratings are exceeded when using this product. 6.3 recommended operating conditions table 6-2. recommended operating conditions parameter symbol conditions min typ max unit operating voltage v dd 3.0 3.3 3.6 v input voltage v i except dp/dn pin 0 v dd v dp/dn input voltage v iu 03.3v 6.4 pin capacitance table 6-3. pin capacitance parameter symbol conditions min max unit input capacitance, 5-v buffer c i 912pf output capacitance, 5-v buffer c o 912pf i/o capacitance, 5-v buffer c io 912pf pci clock input pin capacitance c clk 912pf pci idsel input pin capacitance c idsel 8pf pin inductance l pin 20 nh dpx/dnx pin capacitance c in v dd = 0 v, t a = 25c fc = 1 mhz unmeasured pins returned to 0 v 20 pf
chapter 6 electrical characteristics 79 6.5 dc characteristics (v dd = 3.0 v to 3.6 v, t a = 0 to +70 c) table 6-4. dc characteristics parameter symbol conditions min max unit i ddsl pci/usb clock is stopped, rcvbe = l 300 m a static current consumption i ddsh pci/usb clock is stopped, rcvbe = h 8 ma table 6-5. dc characteristics (pci interface block) parameter symbol conditions min max unit high-level input voltage v ih 0.5 v dd v dd + 0.5 v low-level input voltage v il - 0.5 0.3 v dd v input leakage current i il 0 < v in < v dd 10 m a high-level output voltage v oh i out = - 500 m a 0.9 v dd v low-level output voltage v ol i out = 1500 m a 0.1 v dd v
chapter 6 electrical characteristics 80 figure 6-1. v o vs. i o (pci buffer) (a) v ol vs i ol (v dd = 3.0 v) 3 2 1 0 0 50 100 150 200 i ol (ma) v ol (v) remark min value (process = worst, t a = 70 c), max value (process = best, t a = 0 c) (b) v oh vs i oh (v dd = 3.0 v) 3 2 1 0 0 ?0 ?00 ?50 ?00 i oh (ma) v oh (v) remark min value (process = worst, t a = 70 c), max value (process = best, t a = 0 c)
chapter 6 electrical characteristics 81 (c) v ol vs i ol (v dd = 3.6 v) i ol (ma) v ol (v) 0 50 100 150 200 250 4 3 2 1 0 remark min value (process = worst, t a = 70 c), max value (process = best, t a = 0 c) (d) v oh vs i oh (v dd = 3.6 v) 4 3 2 1 0 0 ?0 ?00 ?50 ?00 i oh (ma) v oh (v) ?50 remark min value (process = worst, t a = 70 c), max value (process = best, t a = 0 c)
chapter 6 electrical characteristics 82 table 6-6. dc characteristics (usb interface block) parameter symbol conditions min max unit data line high impedance leakage current i lo 0 v < v in < 3.3 v 10 m a differential input sensitivity v di ? (d+) - (d - ) ? 0.2 v common mode voltage v cm 0.8 2.5 v single-ended 0 reception threshold v se 0.8 2.0 v high-level output voltage v oh r l of 15 k w to gnd 2.8 3.6 v low-level output voltage v ol r l of 1.5 k w to 3.6 v 0.3 v output signal crossover point voltage v crs 1.3 2.0 v output pin impedance z drv 28 43 w remark the output pin impedance is a value for discrete buffers. in other words, an external series resistance is not required. figure 6-2. v cm (common mode voltage) vs. v di (differential input sensitivity) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 1.0 0.8 0.6 0.4 0.2 0.0 common mode input voltage (v) minimum differential sensitivity (v)
chapter 6 electrical characteristics 83 table 6-7. dc characteristics (control pin block) parameter symbol conditions min max unit high-level input voltage 5-v buffer v ih 2.0 5.5 v low-level input voltage 5-v buffer v il 00.8v positive trigger voltage 5-v buffer v p 2.2 2.55 v negative trigger voltage 5-v buffer v n 0.84 1.01 v hysteresis voltage 5-v buffer v h 1.1 1.5 v off-state output current 5-v buffer i oz v o = v dd or gnd 14 m a input leakage current 5-v buffer i il v o = v dd or gnd 10 m a high-level output current 5-v buffer i oh v o = 0.4 v - 3.0 ma low-level output current 5-v buffer i ol v o = v dd - 0.4 v v o = v dd - 0.4 v 12.0 6.0 ma ma output run-off current 5-v buffer i r v pu = 5.5 v, r pu = 2 k w v o = 3.0 v 14 m a 6.6 power consumption table 6-8. power consumption characteristics parameter symbol conditions typ unit p wd0_o device state = d0, usb = operational 500 mw p wd0_s device state = d0, usb = suspend/reset 150 mw p wd2 device state = d2, usb = suspend/reset 100 mw power consumption p wd3 device state = d3, usb = reset 100 mw remark when the device state = d0, the clock is defined as it is during normal operation. when the device state = d2 or d3, the pci clock is defined as when it is suspended. 6.7 system clock ratings table 6-9. system clock ratings parameter symbol ratings unit clock frequency f clk 48 500 ppm mhz clock duty cycle t duty 10 % input rise time t r 5 (from 0.4 v to 2.4 v) ns input fall time t f 5 (from 2.4 v to 0.4 v) ns
chapter 6 electrical characteristics 84 6.8 ac characteristics (v dd = 3.0 v to 3.6 v, t a = 0 to +70 c) table 6-10. ac characteristics (pci interface block) parameter symbol conditions min max unit pci clock cycle time t cyc 30 ns pci clock pulse, high-level width t high 11 ns pci clock pulse, low-level width t low 11 ns pci clock, rise slew rate s cr 0.2 v dd to 0.6 v dd 14v/ns pci clock, fall slew rate s cf 0.2 v dd to 0.6 v dd 14v/ns pci reset active time (vs. power supply stability) t rst 1ms pci reset active time (vs. clk start) t rst-clk 100 m s output float delay time (vs. rst )t rst-off 40 ns pci reset rise slew rate s rr 50 mv/ns pci bus signal output time (vs. pclk - ) note 1 t val t.b.d ns pci point-to-point signal output time (vs. pclk - ) note 1 t val (ptp) req t.b.d ns output delay time (vs. pclk - )t on t.b.d ns output float delay time (vs. pclk - )t off t.b.d ns pci output rise slew rate note 2 slew r 0.2 v dd to 0.6 v dd 14v/ns pci output fall slew rate note 2 slew f 0.2 v dd to 0.6 v dd 14v/ns input setup time (vs. pclk - )t su t.b.d ns point-to-point input setup time (vs. pclk - ) t su (ptp) gnt t.b.d ns input hold time t h t.b.d ns pci clock reset allowable time (vs. crun ) t crun-clk 5 m s gnt assert allowable time (vs. crun )t crun-gnt vs. iso transaction that is at least 64 bytes in length 7 m s inta, smi, wake cancellation time t intc from when register is set 170 ns
chapter 6 electrical characteristics 85 notes 1. the measurement conditions for tval are as follows. 1/2 in.max 1/2 in.max pin 1 k w 1 k w 10 pf 10 pf v cc 1/2 in.max 1/2 in.max pin 25 w 25 w 10 pf 10 pf v cc (a) rise (min) (c) rise (max) (d) fall (max) (b) fall (min) 2. the measurement conditions for the pci output slew rate are the same as (a) and (b) above.
chapter 6 electrical characteristics 86 table 6-11. ac characteristics (usb interface block) parameter symbol conditions min max unit disconnect decision time t dis 2.5 m s connect decision time t con 2.5 m s rise time full speed low speed t r c l = 50 pf c l = 50 pf c l = 350 pf 4 75 20 300 ns ns ns fall time full speed low speed t f c l = 50 pf c l = 50 pf c l = 350 pf 4 75 20 300 ns ns ns rise/fall matching full speed low speed t rfm (tr/tf) (tr/tf) 90 80 110 120 % % data rate full speed low speed t drate 11.97 1.4775 12.03 1.5225 mbs mbs frame time interval t frame 0.9995 1.0005 ms jitter generated by differential driver full speed next transition paired transition low speed next transition paired transition t dj1 t dj2 t ddj1 t ddj2 - 3.5 - 4.0 - 75 - 45 3.5 4.0 75 45 ns ns ns ns transmitter eop pulse width full speed low speed t eopt 160 1.25 175 1.50 ns m s eop pulse width skew full speed low speed t deop - 2 - 40 5 100 ns ns differential receivers allowable jitter full speed next transition paired transition low speed next transition paired transition t jr1 t jr2 t ujr1 t ujr2 - 18.5 - 9 - 152 - 200 18.5 9 152 200 ns ns ns ns receiver eop pulse width full speed rejection value acceptance value low speed note rejection value acceptance value t eopr1 t eopr2 t eopr1 t eopr2 40 > 40 330 > 330 ns ns ns ns note this applies up until the eof1 token that defines the end of the frame in the hub. the rated full speed is applied between eof1 and eof2.
87 chapter 7 timing charts 7.1 pci clock figure 7-1. pci clock waveforms t high t cyc t low 0.6 v dd 0.5 v dd 0.4 v dd 0.3 v dd 0.2 v dd 0.4 v dd , p-to-p (minimum) 7.2 pci reset figure 7-2. pci reset waveforms vaild pclk pwr_good rst pci signals 100 ms (typ) t rst t rst-clk t rst-off
chapter 7 timing charts 88 7.3 pci output timing figure 7-3. pci output timing t val, t val (ptp) 0.4 v dd 0.615 v dd (falling edge) 0.285 v dd (rising edge) pclk output delay output 0.6 v dd 0.2 v dd t on t off 7.4 pci input timing figure 7-4. pci input timing 0.4 v dd 0.4 v dd 0.4 v dd 0.6 v dd 0.6 v dd 0.2 v dd 0.2 v dd 0.4 v dd inputs valid t h t su, t su (ptp) output delay clk 7.5 pci clock reset figure 7-5. pci clock reset t crun-clk crun pclk
chapter 7 timing charts 89 7.6 crun vs. gnt figure 7-6. crun vs. gnt t crun-gnt crun req gnt 7.7 usb device disconnect detection figure 7-7. usb device disconnect detection gnd t dis device disconnected disconnect detected v oh (min) v se (max) v se (min) v ol (max) 7.8 usb full speed device connect detection figure 7-8. usb full speed device connect detection v oh (min) v se (max) v se (min) v ol (max) gnd device connected d + d e t con connect detected
chapter 7 timing charts 90 7.9 usb low speed device connect detection figure 7-9. usb low speed device connect detection v oh (min) v se (max) v se (min) v ol (max) gnd device connected d e d + t con connect detected 7.10 usb signal rise/fall timing figure 7-10. usb signal rise/fall timing c l c l rise time t r differential data lines t f fall time 10% 10% 90% 90% 7.11 usb differential signal figure 7-11. usb differential signal n * t period +t xjr1 n * t period +t xjr2 next transitions paired transitions differential data lines t period = 1/t drate crossover points
chapter 7 timing charts 91 7.12 usb eop signal figure 7-12. usb eop signal t eopt , t eopr1 , t eopr2 n * t period +t deop differential data lines t period = 1/t drate crossover point crossover point extended 7.13 usb differential receiver allowable jitter figure 7-13. usb differential receiver allowable jitter capacitance next transitions n * t period+ t jr1 paired transitions n * t period+ t jr2 t jr t jr1 t jr2 differential data lines t period = 1/t drate
92 [memo]
93 chapter 8 usb host controller use method 8.1 usb host controller peripheral circuit example this usb hc can be generally divided into four blocks: the pci interface block, usb interface block, legacy interface block, and test pin block. since the pci interface block complies with the pci local bus specification revision 2.1 and pci mobile design guide revision 1.0 , refer to these specifications before designing external circuits or peripheral circuits. the test pin block should be left with all pins unconnected on the board. the following diagrams show a peripheral circuit example in which this host controller is mounted onto an add-in board. the circuits in this example are for reference only: they are not guaranteed as peripheral circuits. figure 8-1. circuit example of usb interface block v cc 15 k 15 k 15 k 15 k 52 53 55 56 57 59 dn1 dp1 ppon1 dn2 dp2 ppon2 oci1 oci2 54 58 usb - hc cn1 usbconn dn dp gnd 1 2 3 4 v cc cn2 usbconn dn dp gnd 1 2 3 4 v cc v cc v cc + + led led + + g s d g s d
chapter 8 usb host controller use method 94 figure 8-2. circuit example of legacy interface block a20s iro2 iro1 iri2 iri1 legc at 82 81 80 72 71 74 79 45 jp2 jp1 jp3 v cc crun rcvbe v cc 10 k usb - hc 73 the jumper settings are shown below. table 8-1. jumper settings pin no legacy legacy clkrun a20s open a20s iri1 low iri1 iri2 low iri2 iro1 open iro1 iro2 open iro2 legc low high at low high crun low low clkrun#
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